Skip to content

Commit 3d53878

Browse files
aokblastaokblast
authored
Merge branch 'main' into support/add_mmap_backend_when_possible
2 parents a9d7f6c + a9ca220 commit 3d53878

File tree

263 files changed

+6346
-4792
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

263 files changed

+6346
-4792
lines changed

‎.github/new-prs-labeler.yml‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1121,3 +1121,6 @@ tablegen:
11211121
- llvm/include/TableGen/**
11221122
- llvm/lib/TableGen/**
11231123
- llvm/utils/TableGen/**
1124+
1125+
infrastructure:
1126+
- .ci/**

‎.github/workflows/llvm-tests.yml‎ renamed to ‎.github/workflows/llvm-abi-tests.yml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
name: LLVM Tests
1+
name: LLVM ABI Tests
22

33
permissions:
44
contents: read

‎clang/docs/ReleaseNotes.rst‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -123,6 +123,9 @@ AST Dumping Potentially Breaking Changes
123123

124124
``__atomic_test_and_set(p, 0)``
125125

126+
- Pretty-printing of templates with inherited (i.e. specified in a previous
127+
redeclaration) default arguments has been fixed.
128+
126129
Clang Frontend Potentially Breaking Changes
127130
-------------------------------------------
128131
- Members of anonymous unions/structs are now injected as ``IndirectFieldDecl``
@@ -250,6 +253,8 @@ Non-comprehensive list of changes in this release
250253

251254
- ``__builtin_assume_dereferenceable`` now accepts non-constant size operands.
252255

256+
- Fixed a crash when the second argument to ``__builtin_assume_aligned`` was not constant (#GH161314)
257+
253258
New Compiler Flags
254259
------------------
255260
- New option ``-fno-sanitize-debug-trap-reasons`` added to disable emitting trap reasons into the debug info when compiling with trapping UBSan (e.g. ``-fsanitize-trap=undefined``).
@@ -452,6 +457,7 @@ Bug Fixes to AST Handling
452457

453458
Miscellaneous Bug Fixes
454459
^^^^^^^^^^^^^^^^^^^^^^^
460+
- Fixed missing diagnostics of ``diagnose_if`` on templates involved in initialization. (#GH160776)
455461

456462
Miscellaneous Clang Crashes Fixed
457463
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

‎clang/include/clang/Basic/BuiltinsNVPTX.td‎

Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -579,11 +579,35 @@ def __nvvm_ff2bf16x2_rn : NVPTXBuiltinSMAndPTX<"_Vector<2, __bf16>(float, float)
579579
def __nvvm_ff2bf16x2_rn_relu : NVPTXBuiltinSMAndPTX<"_Vector<2, __bf16>(float, float)", SM_80, PTX70>;
580580
def __nvvm_ff2bf16x2_rz : NVPTXBuiltinSMAndPTX<"_Vector<2, __bf16>(float, float)", SM_80, PTX70>;
581581
def __nvvm_ff2bf16x2_rz_relu : NVPTXBuiltinSMAndPTX<"_Vector<2, __bf16>(float, float)", SM_80, PTX70>;
582+
def __nvvm_ff2bf16x2_rs :
583+
NVPTXBuiltinSMAndPTX<"_Vector<2, __bf16>(float, float, uint32_t)",
584+
SM<"100a", [SM_103a]>, PTX87>;
585+
def __nvvm_ff2bf16x2_rs_relu :
586+
NVPTXBuiltinSMAndPTX<"_Vector<2, __bf16>(float, float, uint32_t)",
587+
SM<"100a", [SM_103a]>, PTX87>;
588+
def __nvvm_ff2bf16x2_rs_satfinite :
589+
NVPTXBuiltinSMAndPTX<"_Vector<2, __bf16>(float, float, uint32_t)",
590+
SM<"100a", [SM_103a]>, PTX87>;
591+
def __nvvm_ff2bf16x2_rs_relu_satfinite :
592+
NVPTXBuiltinSMAndPTX<"_Vector<2, __bf16>(float, float, uint32_t)",
593+
SM<"100a", [SM_103a]>, PTX87>;
582594

583595
def __nvvm_ff2f16x2_rn : NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(float, float)", SM_80, PTX70>;
584596
def __nvvm_ff2f16x2_rn_relu : NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(float, float)", SM_80, PTX70>;
585597
def __nvvm_ff2f16x2_rz : NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(float, float)", SM_80, PTX70>;
586598
def __nvvm_ff2f16x2_rz_relu : NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(float, float)", SM_80, PTX70>;
599+
def __nvvm_ff2f16x2_rs :
600+
NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(float, float, uint32_t)",
601+
SM<"100a", [SM_103a]>, PTX87>;
602+
def __nvvm_ff2f16x2_rs_relu :
603+
NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(float, float, uint32_t)",
604+
SM<"100a", [SM_103a]>, PTX87>;
605+
def __nvvm_ff2f16x2_rs_satfinite :
606+
NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(float, float, uint32_t)",
607+
SM<"100a", [SM_103a]>, PTX87>;
608+
def __nvvm_ff2f16x2_rs_relu_satfinite :
609+
NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(float, float, uint32_t)",
610+
SM<"100a", [SM_103a]>, PTX87>;
587611

588612
def __nvvm_f2bf16_rn : NVPTXBuiltinSMAndPTX<"__bf16(float)", SM_80, PTX70>;
589613
def __nvvm_f2bf16_rn_relu : NVPTXBuiltinSMAndPTX<"__bf16(float)", SM_80, PTX70>;
@@ -616,6 +640,19 @@ def __nvvm_e4m3x2_to_f16x2_rn_relu : NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(sh
616640
def __nvvm_e5m2x2_to_f16x2_rn : NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(short)", SM_89, PTX81>;
617641
def __nvvm_e5m2x2_to_f16x2_rn_relu : NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(short)", SM_89, PTX81>;
618642

643+
def __nvvm_f32x4_to_e4m3x4_rs_satfinite :
644+
NVPTXBuiltinSMAndPTX<"_Vector<4, char>(_Vector<4, float>, uint32_t)",
645+
SM<"100a", [SM_103a]>, PTX87>;
646+
def __nvvm_f32x4_to_e4m3x4_rs_relu_satfinite :
647+
NVPTXBuiltinSMAndPTX<"_Vector<4, char>(_Vector<4, float>, uint32_t)",
648+
SM<"100a", [SM_103a]>, PTX87>;
649+
def __nvvm_f32x4_to_e5m2x4_rs_satfinite :
650+
NVPTXBuiltinSMAndPTX<"_Vector<4, char>(_Vector<4, float>, uint32_t)",
651+
SM<"100a", [SM_103a]>, PTX87>;
652+
def __nvvm_f32x4_to_e5m2x4_rs_relu_satfinite :
653+
NVPTXBuiltinSMAndPTX<"_Vector<4, char>(_Vector<4, float>, uint32_t)",
654+
SM<"100a", [SM_103a]>, PTX87>;
655+
619656
def __nvvm_ff_to_e2m3x2_rn_satfinite : NVPTXBuiltinSMAndPTX<"short(float, float)", SM<"100a", [SM_101a, SM_120a]>, PTX86>;
620657
def __nvvm_ff_to_e2m3x2_rn_relu_satfinite : NVPTXBuiltinSMAndPTX<"short(float, float)", SM<"100a", [SM_101a, SM_120a]>, PTX86>;
621658
def __nvvm_ff_to_e3m2x2_rn_satfinite : NVPTXBuiltinSMAndPTX<"short(float, float)", SM<"100a", [SM_101a, SM_120a]>, PTX86>;
@@ -626,12 +663,32 @@ def __nvvm_e2m3x2_to_f16x2_rn_relu : NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(sh
626663
def __nvvm_e3m2x2_to_f16x2_rn : NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(short)", SM<"100a", [SM_101a, SM_120a]>, PTX86>;
627664
def __nvvm_e3m2x2_to_f16x2_rn_relu : NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(short)", SM<"100a", [SM_101a, SM_120a]>, PTX86>;
628665

666+
def __nvvm_f32x4_to_e2m3x4_rs_satfinite :
667+
NVPTXBuiltinSMAndPTX<"_Vector<4, char>(_Vector<4, float>, uint32_t)",
668+
SM<"100a", [SM_103a]>, PTX87>;
669+
def __nvvm_f32x4_to_e2m3x4_rs_relu_satfinite :
670+
NVPTXBuiltinSMAndPTX<"_Vector<4, char>(_Vector<4, float>, uint32_t)",
671+
SM<"100a", [SM_103a]>, PTX87>;
672+
def __nvvm_f32x4_to_e3m2x4_rs_satfinite :
673+
NVPTXBuiltinSMAndPTX<"_Vector<4, char>(_Vector<4, float>, uint32_t)",
674+
SM<"100a", [SM_103a]>, PTX87>;
675+
def __nvvm_f32x4_to_e3m2x4_rs_relu_satfinite :
676+
NVPTXBuiltinSMAndPTX<"_Vector<4, char>(_Vector<4, float>, uint32_t)",
677+
SM<"100a", [SM_103a]>, PTX87>;
678+
629679
def __nvvm_ff_to_e2m1x2_rn_satfinite : NVPTXBuiltinSMAndPTX<"short(float, float)", SM<"100a", [SM_101a, SM_120a]>, PTX86>;
630680
def __nvvm_ff_to_e2m1x2_rn_relu_satfinite : NVPTXBuiltinSMAndPTX<"short(float, float)", SM<"100a", [SM_101a, SM_120a]>, PTX86>;
631681

632682
def __nvvm_e2m1x2_to_f16x2_rn : NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(short)", SM<"100a", [SM_101a, SM_120a]>, PTX86>;
633683
def __nvvm_e2m1x2_to_f16x2_rn_relu : NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(short)", SM<"100a", [SM_101a, SM_120a]>, PTX86>;
634684

685+
def __nvvm_f32x4_to_e2m1x4_rs_satfinite :
686+
NVPTXBuiltinSMAndPTX<"short(_Vector<4, float>, uint32_t)",
687+
SM<"100a", [SM_103a]>, PTX87>;
688+
def __nvvm_f32x4_to_e2m1x4_rs_relu_satfinite :
689+
NVPTXBuiltinSMAndPTX<"short(_Vector<4, float>, uint32_t)",
690+
SM<"100a", [SM_103a]>, PTX87>;
691+
635692
def __nvvm_ff_to_ue8m0x2_rz : NVPTXBuiltinSMAndPTX<"short(float, float)", SM<"100a", [SM_101a, SM_120a]>, PTX86>;
636693
def __nvvm_ff_to_ue8m0x2_rz_satfinite : NVPTXBuiltinSMAndPTX<"short(float, float)", SM<"100a", [SM_101a, SM_120a]>, PTX86>;
637694
def __nvvm_ff_to_ue8m0x2_rp : NVPTXBuiltinSMAndPTX<"short(float, float)", SM<"100a", [SM_101a, SM_120a]>, PTX86>;

‎clang/include/clang/Basic/LangOptions.def‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -245,7 +245,6 @@ LANGOPT(HLSLStrictAvailability, 1, 0, NotCompatible,
245245
LANGOPT(HLSLSpvUseUnknownImageFormat, 1, 0, NotCompatible, "For storage images and texel buffers, sets the default format to 'Unknown' when not specified via the `vk::image_format` attribute. If this option is not used, the format is inferred from the resource's data type.")
246246

247247
LANGOPT(CUDAIsDevice , 1, 0, NotCompatible, "compiling for CUDA device")
248-
LANGOPT(CUDAAllowVariadicFunctions, 1, 0, NotCompatible, "allowing variadic functions in CUDA device code")
249248
LANGOPT(CUDAHostDeviceConstexpr, 1, 1, NotCompatible, "treating unattributed constexpr functions as __host__ __device__")
250249
LANGOPT(GPUDeviceApproxTranscendentals, 1, 0, NotCompatible, "using approximate transcendental functions")
251250
LANGOPT(GPURelocatableDeviceCode, 1, 0, NotCompatible, "generate relocatable device code")

‎clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -178,9 +178,10 @@ class CIRBaseBuilderTy : public mlir::OpBuilder {
178178
}
179179

180180
mlir::Value createComplexImag(mlir::Location loc, mlir::Value operand) {
181-
auto operandTy = mlir::cast<cir::ComplexType>(operand.getType());
182-
return cir::ComplexImagOp::create(*this, loc, operandTy.getElementType(),
183-
operand);
181+
auto resultType = operand.getType();
182+
if (auto complexResultType = mlir::dyn_cast<cir::ComplexType>(resultType))
183+
resultType = complexResultType.getElementType();
184+
return cir::ComplexImagOp::create(*this, loc, resultType, operand);
184185
}
185186

186187
cir::LoadOp createLoad(mlir::Location loc, mlir::Value ptr,

‎clang/include/clang/CIR/Dialect/IR/CIROps.td‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3308,18 +3308,20 @@ def CIR_ComplexRealOp : CIR_Op<"complex.real", [Pure]> {
33083308
def CIR_ComplexImagOp : CIR_Op<"complex.imag", [Pure]> {
33093309
let summary = "Extract the imaginary part of a complex value";
33103310
let description = [{
3311-
`cir.complex.imag` operation takes an operand of `!cir.complex` type and
3312-
yields the imaginary part of it.
3311+
`cir.complex.imag` operation takes an operand of `!cir.complex`, `!cir.int`
3312+
or `!cir.float`. If the operand is `!cir.complex`, the imag part of it will
3313+
be returned, otherwise a zero value will be returned.
33133314

33143315
Example:
33153316

33163317
```mlir
3317-
%1 = cir.complex.imag %0 : !cir.complex<!cir.float> -> !cir.float
3318+
%imag = cir.complex.imag %complex : !cir.complex<!cir.float> -> !cir.float
3319+
%imag = cir.complex.imag %scalar : !cir.float -> !cir.float
33183320
```
33193321
}];
33203322

33213323
let results = (outs CIR_AnyIntOrFloatType:$result);
3322-
let arguments = (ins CIR_ComplexType:$operand);
3324+
let arguments = (ins CIR_AnyComplexOrIntOrFloatType:$operand);
33233325

33243326
let assemblyFormat = [{
33253327
$operand `:` qualified(type($operand)) `->` qualified(type($result))

‎clang/include/clang/Driver/Options.td‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8733,8 +8733,7 @@ def fcuda_include_gpubinary : Separate<["-"], "fcuda-include-gpubinary">,
87338733
HelpText<"Incorporate CUDA device-side binary into host object file.">,
87348734
MarshallingInfoString<CodeGenOpts<"CudaGpuBinaryFileName">>;
87358735
def fcuda_allow_variadic_functions : Flag<["-"], "fcuda-allow-variadic-functions">,
8736-
HelpText<"Allow variadic functions in CUDA device code.">,
8737-
MarshallingInfoFlag<LangOpts<"CUDAAllowVariadicFunctions">>;
8736+
HelpText<"Deprecated; Allow variadic functions in CUDA device code.">;
87388737
def fno_cuda_host_device_constexpr : Flag<["-"], "fno-cuda-host-device-constexpr">,
87398738
HelpText<"Don't treat unattributed constexpr functions as __host__ __device__.">,
87408739
MarshallingInfoNegativeFlag<LangOpts<"CUDAHostDeviceConstexpr">>;

‎clang/include/clang/Sema/SemaConcept.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -257,6 +257,7 @@ struct NormalizedConstraint {
257257
case ConstraintKind::FoldExpanded:
258258
return FoldExpanded.Pattern->getBeginLoc();
259259
}
260+
llvm_unreachable("Unknown ConstraintKind enum");
260261
}
261262

262263
SourceLocation getEndLoc() const {
@@ -270,6 +271,7 @@ struct NormalizedConstraint {
270271
case ConstraintKind::FoldExpanded:
271272
return FoldExpanded.Pattern->getEndLoc();
272273
}
274+
llvm_unreachable("Unknown ConstraintKind enum");
273275
}
274276

275277
SourceRange getSourceRange() const { return {getBeginLoc(), getEndLoc()}; }

‎clang/lib/AST/ByteCode/InterpBuiltin.cpp‎

Lines changed: 9 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -736,25 +736,6 @@ static bool interp__builtin_expect(InterpState &S, CodePtr OpPC,
736736
return true;
737737
}
738738

739-
/// rotateleft(value, amount)
740-
static bool interp__builtin_rotate(InterpState &S, CodePtr OpPC,
741-
const InterpFrame *Frame,
742-
const CallExpr *Call, bool Right) {
743-
APSInt Amount = popToAPSInt(S, Call->getArg(1));
744-
APSInt Value = popToAPSInt(S, Call->getArg(0));
745-
746-
APSInt Result;
747-
if (Right)
748-
Result = APSInt(Value.rotr(Amount.urem(Value.getBitWidth())),
749-
/*IsUnsigned=*/true);
750-
else // Left.
751-
Result = APSInt(Value.rotl(Amount.urem(Value.getBitWidth())),
752-
/*IsUnsigned=*/true);
753-
754-
pushInteger(S, Result, Call->getType());
755-
return true;
756-
}
757-
758739
static bool interp__builtin_ffs(InterpState &S, CodePtr OpPC,
759740
const InterpFrame *Frame,
760741
const CallExpr *Call) {
@@ -2796,7 +2777,7 @@ static bool interp__builtin_ia32_pshuf(InterpState &S, CodePtr OpPC,
27962777
unsigned LaneBase = (Idx / LaneElts) * LaneElts;
27972778
unsigned LaneIdx = Idx % LaneElts;
27982779
unsigned SrcIdx = Idx;
2799-
unsigned Sel = (Ctl >> (2 * LaneIdx)) & 0x3;
2780+
unsigned Sel = (Ctl >> (2 * (LaneIdx & 0x3))) & 0x3;
28002781
if (ElemBits == 32) {
28012782
SrcIdx = LaneBase + Sel;
28022783
} else {
@@ -2805,8 +2786,6 @@ static bool interp__builtin_ia32_pshuf(InterpState &S, CodePtr OpPC,
28052786
if (!IsShufHW && !InHigh) {
28062787
SrcIdx = LaneBase + Sel;
28072788
} else if (IsShufHW && InHigh) {
2808-
unsigned Rel = LaneIdx - HalfSize;
2809-
Sel = (Ctl >> (2 * Rel)) & 0x3;
28102789
SrcIdx = LaneBase + HalfSize + Sel;
28112790
}
28122791
}
@@ -3162,7 +3141,10 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const CallExpr *Call,
31623141
case Builtin::BI_rotl:
31633142
case Builtin::BI_lrotl:
31643143
case Builtin::BI_rotl64:
3165-
return interp__builtin_rotate(S, OpPC, Frame, Call, /*Right=*/false);
3144+
return interp__builtin_elementwise_int_binop(
3145+
S, OpPC, Call, [](const APSInt &Value, const APSInt &Amount) -> APInt {
3146+
return Value.rotl(Amount);
3147+
});
31663148

31673149
case Builtin::BI__builtin_rotateright8:
31683150
case Builtin::BI__builtin_rotateright16:
@@ -3173,7 +3155,10 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const CallExpr *Call,
31733155
case Builtin::BI_rotr:
31743156
case Builtin::BI_lrotr:
31753157
case Builtin::BI_rotr64:
3176-
return interp__builtin_rotate(S, OpPC, Frame, Call, /*Right=*/true);
3158+
return interp__builtin_elementwise_int_binop(
3159+
S, OpPC, Call, [](const APSInt &Value, const APSInt &Amount) -> APInt {
3160+
return Value.rotr(Amount);
3161+
});
31773162

31783163
case Builtin::BI__builtin_ffs:
31793164
case Builtin::BI__builtin_ffsl:

0 commit comments

Comments
 (0)