fixup! tablegen formatting

Author: topperc

llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td

@@ -225,7 +225,7 @@ let Predicates = [HasVendorXSfmmbase] in {
   def SF_VSETTM : SFInstSetSingle<(outs GPR:$rd), (ins GPR:$rs1), 0b00001,
                                   "sf.vsettm", "$rd, $rs1">;
   def SF_VSETTK : SFInstSetSingle<(outs GPR:$rd), (ins GPR:$rs1), 0b00010,
-                                   "sf.vsettk", "$rd, $rs1">;
+                                  "sf.vsettk", "$rd, $rs1">;
   def SF_VTDISCARD : SFInstVtDiscard<"sf.vtdiscard">;
 
   def SF_VTMV_V_T : SFInstTileMoveOp<0b010000, (outs VR:$vd), (ins GPR:$rs1),
@@ -280,7 +280,7 @@ let Uses = [FRM], mayRaiseFPException = true in {
 
 class VPseudoSF_VTileLoad
     : RISCVVPseudo<(outs), (ins GPR:$rs2, GPR:$rs1, AVL:$atn, ixlenimm:$sew,
-                            ixlenimm:$twiden)> {
+                                ixlenimm:$twiden)> {
   let mayLoad = 1;
   let mayStore = 0;
   let HasVLOp = 1; // Tn
@@ -291,7 +291,7 @@ class VPseudoSF_VTileLoad
 
 class VPseudoSF_VTileStore
     : RISCVVPseudo<(outs), (ins GPR:$rs2, GPR:$rs1, AVL:$atn, ixlenimm:$sew,
-                            ixlenimm:$twiden)> {
+                                ixlenimm:$twiden)> {
   let mayLoad = 0;
   let mayStore = 1;
   let HasVLOp = 1; // Tn
@@ -302,7 +302,7 @@ class VPseudoSF_VTileStore
 
 class VPseudoSF_VTileMove_V_T
     : RISCVVPseudo<(outs VRM8:$vd), (ins GPR:$rs1, AVL:$atn, ixlenimm:$sew,
-                                     ixlenimm:$twiden)> {
+                                         ixlenimm:$twiden)> {
   let mayLoad = 0;
   let mayStore = 0;
   let HasVLOp = 1; // Tn
@@ -313,7 +313,7 @@ class VPseudoSF_VTileMove_V_T
 
 class VPseudoSF_VTileMove_T_V
     : RISCVVPseudo<(outs), (ins GPR:$rs1, VRM8:$vs2, AVL:$atn, ixlenimm:$sew,
-                            ixlenimm:$twiden)> {
+                                ixlenimm:$twiden)> {
   let mayLoad = 0;
   let mayStore = 0;
   let HasVLOp = 1; // Tn
@@ -325,7 +325,7 @@ class VPseudoSF_VTileMove_T_V
 class VPseudoSF_MatMul<RegisterClass mtd_class>
     : RISCVVPseudo<(outs),
                    (ins mtd_class:$rd, VRM8:$vs2, VRM8:$vs1, AVL:$atm, AVL:$atn,
-                    AVL:$atk, ixlenimm:$sew, ixlenimm:$twiden)> {
+                        AVL:$atk, ixlenimm:$sew, ixlenimm:$twiden)> {
   let mayLoad = 0;
   let mayStore = 0;
   let HasTmOp = 1;
@@ -339,8 +339,8 @@ class VPseudoSF_MatMul<RegisterClass mtd_class>
 class VPseudoSF_MatMul_FRM<RegisterClass mtd_class>
     : RISCVVPseudo<(outs),
                    (ins mtd_class:$rd, VRM8:$vs2, VRM8:$vs1, ixlenimm:$frm,
-                    AVL:$atm, AVL:$atn, AVL:$atk, ixlenimm:$sew,
-                    ixlenimm:$twiden), []> {
+                        AVL:$atm, AVL:$atn, AVL:$atk, ixlenimm:$sew,
+                        ixlenimm:$twiden), []> {
   let mayLoad = 0;
   let mayStore = 0;
   let HasTmOp = 1;
@@ -359,7 +359,7 @@ let Defs = [VL, VTYPE] in {
   def PseudoSF_VSETTNT
       : Pseudo<(outs GPR:$rd),
                (ins GPRNoX0:$rs1, XSfmmVTypeOp:$vtypei), []>,
-        PseudoInstExpansion<(VSETVLI GPR:$rd, GPR:$rs1, VTypeIOp11:$vtypei)>, 
+        PseudoInstExpansion<(VSETVLI GPR:$rd, GPR:$rs1, VTypeIOp11:$vtypei)>,
         Sched<[WriteVSETVLI, ReadVSETVLI]>;
   def PseudoSF_VSETTNTX0
       : Pseudo<(outs GPRNoX0:$rd),
@@ -369,17 +369,19 @@ let Defs = [VL, VTYPE] in {
   def PseudoSF_VSETTNTX0X0
       : Pseudo<(outs GPRX0:$rd),
                (ins GPRX0:$rs1, XSfmmVTypeOp:$vtypei), []>,
-        PseudoInstExpansion<(VSETVLI GPR:$rd, GPR:$rs1, VTypeIOp11:$vtypei)>, 
+        PseudoInstExpansion<(VSETVLI GPR:$rd, GPR:$rs1, VTypeIOp11:$vtypei)>,
         Sched<[WriteVSETVLI, ReadVSETVLI]>;
 }
 
 let Defs = [VTYPE], Uses = [VTYPE], HasTWidenOp = 1, HasSEWOp = 1 in {
   def PseudoSF_VSETTM
-      : Pseudo<(outs GPR:$rd), (ins GPR:$rs1, ixlenimm:$log2sew, ixlenimm:$twiden), []>,
+      : Pseudo<(outs GPR:$rd),
+               (ins GPR:$rs1, ixlenimm:$log2sew, ixlenimm:$twiden), []>,
         PseudoInstExpansion<(SF_VSETTM GPR:$rd, GPR:$rs1)>,
         Sched<[WriteVSETVLI, ReadVSETVLI]>;
   def PseudoSF_VSETTK
-      : Pseudo<(outs GPR:$rd), (ins GPR:$rs1, ixlenimm:$logwsew, ixlenimm:$twiden), []>,
+      : Pseudo<(outs GPR:$rd),
+               (ins GPR:$rs1, ixlenimm:$logwsew, ixlenimm:$twiden), []>,
         PseudoInstExpansion<(SF_VSETTK GPR:$rd, GPR:$rs1)>,
         Sched<[WriteVSETVLI, ReadVSETVLI]>;
 }
@@ -412,6 +414,7 @@ let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
   let HasVLOp = 1, HasTmOp = 1, HasTWidenOp = 1, HasSEWOp = 1 in
     def PseudoSF_VTZERO_T
         : RISCVVPseudo<(outs),
-                       (ins TR:$rd, AVL:$atm, AVL:$atn, ixlenimm:$sew, ixlenimm:$twiden)>;
+                       (ins TR:$rd, AVL:$atm, AVL:$atn, ixlenimm:$sew,
+                            ixlenimm:$twiden)>;
   def PseudoSF_VTDISCARD : RISCVVPseudo<(outs), (ins), []>;
 }