add negative tests

Author: Ana Mihajlovic

llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp

@@ -877,7 +877,7 @@ unsigned SIShrinkInstructions::getInverseCompareOpcode(MachineInstr &MI) const {
     return AMDGPU::V_CMP_LE_U32_e64;
   case AMDGPU::V_CMP_LT_U32_e64:
     return AMDGPU::V_CMP_GE_U32_e64;
-    // unsigned 64
+  // unsigned 64
   case AMDGPU::V_CMP_EQ_U64_e64:
     return AMDGPU::V_CMP_NE_U64_e64;
   case AMDGPU::V_CMP_NE_U64_e64:
@@ -956,7 +956,7 @@ unsigned SIShrinkInstructions::getInverseCompareOpcode(MachineInstr &MI) const {
 bool SIShrinkInstructions::shouldSwapCndOperands(
     MachineInstr &MI, SmallVector<MachineOperand *, 4> &UsesToProcess) const {
   auto AllUses = MRI->use_nodbg_operands(MI.getOperand(0).getReg());
-  unsigned Swap = 0, SwapNot = 0;
+  int InstsToSwap = 0;
 
   for (auto &Use : AllUses) {
     MachineInstr *UseInst = Use.getParent();
@@ -972,12 +972,12 @@ bool SIShrinkInstructions::shouldSwapCndOperands(
     bool Src1Imm = Src1.isImm();
 
     if (!Src1Imm && Src0Imm)
-      SwapNot++;
+      InstsToSwap--;
     else if (Src1Imm && !Src0Imm &&
              UseInst->getOperand(1).getImm() == SISrcMods::NONE)
-      Swap++;
+      InstsToSwap++;
   }
-  return (Swap > SwapNot);
+  return (InstsToSwap > 0);
 }
 
 static void swapCndOperands(MachineInstr &MI) {
@@ -994,7 +994,9 @@ static void swapCndOperands(MachineInstr &MI) {
   }
 
   if (Op4.isReg()) {
-    Op2.setReg(Op4.getReg());
+    Op2.ChangeToRegister(Op4.getReg(), Op4.isDef(), Op4.isImplicit(),
+                         Op4.isKill(), Op4.isDead(), Op4.isUndef(),
+                         Op4.isDebug());
     Op2.setSubReg(Op4.getSubReg());
   } else if (Op4.isImm()) {
     Op2.ChangeToImmediate(Op4.getImm());

llvm/test/CodeGen/AMDGPU/shrink-cndmask.ll

@@ -162,6 +162,47 @@ define amdgpu_cs void @test_u32_eq(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out
   ret void
 }
 
+define amdgpu_cs void @test_negative_case(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_negative_case:
+; GCN:       ; %bb.0: ; %.entry
+; GCN-NEXT:    v_cmp_eq_u32_e32 vcc_lo, -1, v0
+; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GCN-NEXT:    v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT:    global_store_b64 v[3:4], v[0:1], off
+; GCN-NEXT:    s_endpgm
+.entry:
+  %vcc = icmp eq i32 %a, -1
+  %val1 = select i1 %vcc, i32 %p, i32 0
+  %val2 = select i1 %vcc, i32 0, i32 %q
+  %ret0 = insertelement <2 x i32> poison, i32 %val1, i32 0
+  %ret1 = insertelement <2 x i32> %ret0, i32 %val2, i32 1
+  store <2 x i32> %ret1, ptr addrspace(1) %out
+  ret void
+}
+
+define amdgpu_cs void @test_mixed(i32 %a, i32 %p, i32 %q, i32 %r, i32 %s, ptr addrspace(1) %out) {
+; GCN-LABEL: test_mixed:
+; GCN:       ; %bb.0: ; %.entry
+; GCN-NEXT:    v_cmp_ne_u32_e32 vcc_lo, -1, v0
+; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GCN-NEXT:    v_cndmask_b32_e64 v1, v2, 0, vcc_lo
+; GCN-NEXT:    v_dual_cndmask_b32 v2, 0, v3 :: v_dual_cndmask_b32 v3, 0, v4
+; GCN-NEXT:    global_store_b128 v[5:6], v[0:3], off
+; GCN-NEXT:    s_endpgm
+.entry:
+  %vcc = icmp eq i32 -1, %a
+  %val1 = select i1 %vcc, i32 0, i32 %p
+  %val2 = select i1 %vcc, i32 %q, i32 0
+  %val3 = select i1 %vcc, i32 0, i32 %r
+  %val4 = select i1 %vcc, i32 0, i32 %s
+  %ret0 = insertelement <4 x i32> poison, i32 %val1, i32 0
+  %ret1 = insertelement <4 x i32> %ret0, i32 %val2, i32 1
+  %ret2 = insertelement <4 x i32> %ret1, i32 %val3, i32 2
+  %ret3 = insertelement <4 x i32> %ret2, i32 %val4, i32 3
+  store <4 x i32> %ret3, ptr addrspace(1) %out
+  ret void
+}
+
 define amdgpu_cs void @test_u32_ne(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out) {
 ; GCN-LABEL: test_u32_ne:
 ; GCN:       ; %bb.0: ; %.entry
@@ -374,6 +415,25 @@ define amdgpu_cs void @test_f32_oeq(float %a, float %p, float %q, ptr addrspace(
   ret void
 }
 
+define amdgpu_cs void @test_f32_negative_modifiers(float %a, float %p, float %q, ptr addrspace(1) %out) {
+; GCN-LABEL: test_f32_negative_modifiers:
+; GCN:       ; %bb.0: ; %.entry
+; GCN-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 2.0, v0
+; GCN-NEXT:    v_cndmask_b32_e64 v0, -v1, 0, vcc_lo
+; GCN-NEXT:    v_cndmask_b32_e64 v1, -v2, 0, vcc_lo
+; GCN-NEXT:    global_store_b64 v[3:4], v[0:1], off
+; GCN-NEXT:    s_endpgm
+.entry:
+  %r = fneg float %p
+  %s = fneg  float %q
+  %vcc = fcmp oeq float 2.0, %a
+  %val1 = select i1 %vcc, float 0.0, float %r
+  %val2 = select i1 %vcc, float 0.0, float %s
+  %ret0 = insertelement <2 x float> poison, float %val1, i32 0
+  %ret1 = insertelement <2 x float> %ret0, float %val2, i32 1
+  store <2 x float> %ret1, ptr addrspace(1) %out
+  ret void
+}
 
 define amdgpu_cs void @test_f32_one(float %a, float %p, float %q, ptr addrspace(1) %out) {
 ; GCN-LABEL: test_f32_one: