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kmclaughlin-armkmclaughlin-arm
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- Removed Multi_Index_FormStrided_Pat classes and reused existing classes
- Removed isReg() check for operand 1 of a copy - Moved loop over FORM_STRIDED_TUPLE operands to new function.
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3 files changed

+52
-66
lines changed

3 files changed

+52
-66
lines changed

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 50 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -8646,6 +8646,55 @@ static bool checkZExtBool(SDValue Arg, const SelectionDAG &DAG) {
86468646
return ZExtBool;
86478647
}
86488648

8649+
bool shouldUseFormStridedPseudo(MachineInstr &MI) {
8650+
MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
8651+
bool UseFormStrided = false;
8652+
unsigned NumOperands =
8653+
MI.getOpcode() == AArch64::FORM_STRIDED_TUPLE_X2_PSEUDO ? 2 : 4;
8654+
8655+
// The FORM_STRIDED_TUPLE pseudo should only be used if the input operands
8656+
// are copy nodes where the source register is in a StridedOrContiguous
8657+
// class. For example:
8658+
// %3:zpr2stridedorcontiguous = LD1B_2Z_IMM_PSEUDO ..
8659+
// %4:zpr = COPY %3.zsub1:zpr2stridedorcontiguous
8660+
// %5:zpr = COPY %3.zsub0:zpr2stridedorcontiguous
8661+
// %6:zpr2stridedorcontiguous = LD1B_2Z_PSEUDO ..
8662+
// %7:zpr = COPY %6.zsub1:zpr2stridedorcontiguous
8663+
// %8:zpr = COPY %6.zsub0:zpr2stridedorcontiguous
8664+
// %9:zpr2mul2 = FORM_STRIDED_TUPLE_X2_PSEUDO %5:zpr, %8:zpr
8665+
8666+
MCRegister SubReg = MCRegister::NoRegister;
8667+
for (unsigned I = 1; I < MI.getNumOperands(); ++I) {
8668+
MachineOperand &MO = MI.getOperand(I);
8669+
assert(MO.isReg() && "Unexpected operand to FORM_STRIDED_TUPLE");
8670+
8671+
MachineOperand *Def = MRI.getOneDef(MO.getReg());
8672+
if (!Def || !Def->isReg() || !Def->getParent()->isCopy()) {
8673+
UseFormStrided = false;
8674+
break;
8675+
}
8676+
8677+
MachineOperand CpyOp = Def->getParent()->getOperand(1);
8678+
MachineOperand *Ld = MRI.getOneDef(CpyOp.getReg());
8679+
unsigned OpSubReg = CpyOp.getSubReg();
8680+
if (SubReg == MCRegister::NoRegister)
8681+
SubReg = OpSubReg;
8682+
if (!Ld || !Ld->isReg() || OpSubReg != SubReg) {
8683+
UseFormStrided = false;
8684+
break;
8685+
}
8686+
8687+
const TargetRegisterClass *RegClass =
8688+
NumOperands == 2 ? &AArch64::ZPR2StridedOrContiguousRegClass
8689+
: &AArch64::ZPR4StridedOrContiguousRegClass;
8690+
8691+
if (MRI.getRegClass(Ld->getReg()) == RegClass)
8692+
UseFormStrided = true;
8693+
}
8694+
8695+
return UseFormStrided;
8696+
}
8697+
86498698
void AArch64TargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
86508699
SDNode *Node) const {
86518700
// Live-in physreg copies that are glued to SMSTART are applied as
@@ -8673,57 +8722,9 @@ void AArch64TargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
86738722

86748723
if (MI.getOpcode() == AArch64::FORM_STRIDED_TUPLE_X2_PSEUDO ||
86758724
MI.getOpcode() == AArch64::FORM_STRIDED_TUPLE_X4_PSEUDO) {
8676-
MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
8677-
bool UseFormStrided = false;
8678-
unsigned Size =
8679-
MI.getOpcode() == AArch64::FORM_STRIDED_TUPLE_X2_PSEUDO ? 2 : 4;
8680-
8681-
// The FORM_STRIDED_TUPLE pseudo should only be used if the input operands
8682-
// are copy nodes where the source register is in a StridedOrContiguous
8683-
// class. For example:
8684-
// %3:zpr2stridedorcontiguous = LD1B_2Z_IMM_PSEUDO ..
8685-
// %4:zpr = COPY %3.zsub1:zpr2stridedorcontiguous
8686-
// %5:zpr = COPY %3.zsub0:zpr2stridedorcontiguous
8687-
// %6:zpr2stridedorcontiguous = LD1B_2Z_PSEUDO ..
8688-
// %7:zpr = COPY %6.zsub1:zpr2stridedorcontiguous
8689-
// %8:zpr = COPY %6.zsub0:zpr2stridedorcontiguous
8690-
// %9:zpr2mul2 = FORM_STRIDED_TUPLE_X2_PSEUDO %5:zpr, %8:zpr
8691-
8692-
SmallVector<unsigned, 4> OpSubRegs;
8693-
for (unsigned I = 1; I < MI.getNumOperands(); ++I) {
8694-
MachineOperand &MO = MI.getOperand(I);
8695-
if (!MO.isReg())
8696-
continue;
8697-
8698-
MachineOperand *Def = MRI.getOneDef(MO.getReg());
8699-
if (!Def || !Def->isReg() || !Def->getParent()->isCopy())
8700-
continue;
8701-
8702-
MachineInstr *Cpy = Def->getParent();
8703-
MachineOperand CpyOp = Cpy->getOperand(1);
8704-
if (!CpyOp.isReg())
8705-
continue;
8706-
8707-
MachineOperand *Ld = MRI.getOneDef(CpyOp.getReg());
8708-
OpSubRegs.push_back(CpyOp.getSubReg());
8709-
if (!Ld || !Ld->isReg())
8710-
continue;
8711-
8712-
const TargetRegisterClass *RegClass =
8713-
Size == 2 ? &AArch64::ZPR2StridedOrContiguousRegClass
8714-
: &AArch64::ZPR4StridedOrContiguousRegClass;
8715-
8716-
if (MRI.getRegClass(Ld->getReg()) == RegClass)
8717-
UseFormStrided = true;
8718-
}
8719-
8720-
// Ensure the operands all use the same subreg index.
8721-
if (!std::equal(OpSubRegs.begin(), OpSubRegs.end(), OpSubRegs.begin()))
8722-
UseFormStrided = false;
8723-
87248725
// If input values to the FORM_STRIDED_TUPLE pseudo aren't copies from a
87258726
// StridedOrContiguous class, fall back on REG_SEQUENCE node.
8726-
if (!UseFormStrided) {
8727+
if (!shouldUseFormStridedPseudo(MI)) {
87278728
static const unsigned SubRegs[] = {AArch64::zsub0, AArch64::zsub1,
87288729
AArch64::zsub2, AArch64::zsub3};
87298730

‎llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,6 @@ def AArch64_restore_zt : SDNode<"AArch64ISD::RESTORE_ZT", SDTypeProfile<0, 2,
2828
def AArch64_save_zt : SDNode<"AArch64ISD::SAVE_ZT", SDTypeProfile<0, 2,
2929
[SDTCisInt<0>, SDTCisPtrTy<1>]>,
3030
[SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
31-
3231
def AArch64CoalescerBarrier
3332
: SDNode<"AArch64ISD::COALESCER_BARRIER", SDTypeProfile<1, 1, []>, [SDNPOptInGlue, SDNPOutGlue]>;
3433

‎llvm/lib/Target/AArch64/SMEInstrFormats.td‎

Lines changed: 2 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -184,26 +184,12 @@ class SME2_ZA_TwoOp_Multi_Index_Pat<string name, SDPatternOperator intrinsic, Op
184184

185185
class SME2_ZA_TwoOp_VG2_Multi_Index_Pat<string name, SDPatternOperator intrinsic, Operand index_ty, ZPRRegOp zpr_ty, ValueType vt,
186186
Operand imm_ty, ComplexPattern tileslice>
187-
: Pat<(intrinsic (i32 (tileslice MatrixIndexGPR32Op8_11:$base, index_ty:$offset)), vt:$Zn1, vt:$Zn2, vt:$Zm, (i32 imm_ty:$i)),
188-
(!cast<Instruction>(name # _PSEUDO) $base, $offset,
189-
(REG_SEQUENCE ZPR2Mul2, vt:$Zn1, zsub0, vt:$Zn2, zsub1), zpr_ty:$Zm, imm_ty:$i)>;
190-
191-
class SME2_ZA_TwoOp_VG2_Multi_Index_FormStrided_Pat<string name, SDPatternOperator intrinsic, Operand index_ty, ZPRRegOp zpr_ty, ValueType vt,
192-
Operand imm_ty, ComplexPattern tileslice>
193187
: Pat<(intrinsic (i32 (tileslice MatrixIndexGPR32Op8_11:$base, index_ty:$offset)), vt:$Zn1, vt:$Zn2, vt:$Zm, (i32 imm_ty:$i)),
194188
(!cast<Instruction>(name # _PSEUDO) $base, $offset,
195189
(FORM_STRIDED_TUPLE_X2_PSEUDO vt:$Zn1,vt:$Zn2), zpr_ty:$Zm, imm_ty:$i)>;
196190

197191
class SME2_ZA_TwoOp_VG4_Multi_Index_Pat<string name, SDPatternOperator intrinsic, Operand index_ty, ZPRRegOp zpr_ty, ValueType vt,
198192
Operand imm_ty, ComplexPattern tileslice>
199-
: Pat<(intrinsic (i32 (tileslice MatrixIndexGPR32Op8_11:$base, index_ty:$offset)),
200-
vt:$Zn1, vt:$Zn2, vt:$Zn3, vt:$Zn4, vt:$Zm, (i32 imm_ty:$i)),
201-
(!cast<Instruction>(name # _PSEUDO) $base, $offset,
202-
(REG_SEQUENCE ZPR4Mul4, vt:$Zn1, zsub0, vt:$Zn2, zsub1, vt:$Zn3, zsub2, vt:$Zn4, zsub3),
203-
zpr_ty:$Zm, imm_ty:$i)>;
204-
205-
class SME2_ZA_TwoOp_VG4_Multi_Index_FormStrided_Pat<string name, SDPatternOperator intrinsic, Operand index_ty, ZPRRegOp zpr_ty, ValueType vt,
206-
Operand imm_ty, ComplexPattern tileslice>
207193
: Pat<(intrinsic (i32 (tileslice MatrixIndexGPR32Op8_11:$base, index_ty:$offset)),
208194
vt:$Zn1, vt:$Zn2, vt:$Zn3, vt:$Zn4, vt:$Zm, (i32 imm_ty:$i)),
209195
(!cast<Instruction>(name # _PSEUDO) $base, $offset,
@@ -2651,7 +2637,7 @@ multiclass sme2_multi_vec_array_vg2_index_32b<string mnemonic, bits<2> sz, bits<
26512637
}
26522638
def _PSEUDO : sme2_za_array_2op_multi_index_pseudo<NAME, sme_elm_idx0_7, multi_vector_ty, vector_ty, VectorIndexS32b_timm, SMEMatrixArray>;
26532639

2654-
def : SME2_ZA_TwoOp_VG2_Multi_Index_FormStrided_Pat<NAME, intrinsic, sme_elm_idx0_7, vector_ty, vt, VectorIndexS32b_timm, tileslice16>;
2640+
def : SME2_ZA_TwoOp_VG2_Multi_Index_Pat<NAME, intrinsic, sme_elm_idx0_7, vector_ty, vt, VectorIndexS32b_timm, tileslice16>;
26552641

26562642
def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm3], $Zn, $Zm$i",
26572643
(!cast<Instruction>(NAME) MatrixOp32:$ZAda, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3,
@@ -2794,7 +2780,7 @@ multiclass sme2_multi_vec_array_vg4_index_32b<string mnemonic, bits<4> op,
27942780

27952781
def _PSEUDO : sme2_za_array_2op_multi_index_pseudo<NAME, sme_elm_idx0_7, multi_vector_ty, vector_ty, VectorIndexS32b_timm, SMEMatrixArray>;
27962782

2797-
def : SME2_ZA_TwoOp_VG4_Multi_Index_FormStrided_Pat<NAME, intrinsic, sme_elm_idx0_7, vector_ty, vt, VectorIndexS32b_timm, tileslice16>;
2783+
def : SME2_ZA_TwoOp_VG4_Multi_Index_Pat<NAME, intrinsic, sme_elm_idx0_7, vector_ty, vt, VectorIndexS32b_timm, tileslice16>;
27982784

27992785
def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm3], $Zn, $Zm$i",
28002786
(!cast<Instruction>(NAME) MatrixOp32:$ZAda, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3,

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