Mark TPREL_ADD as needing R_RISCV_RELAX

lenary · lenary · commit 439939e66498 · 2025-08-07T16:12:25.000-07:00
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -820,6 +820,7 @@ static bool fixupGetsRelaxRelocation(const MCFixupKind Kind) {
   case ELF::R_RISCV_TPREL_LO12_I:
   case ELF::R_RISCV_TPREL_LO12_S:
   case ELF::R_RISCV_TPREL_HI20:
+  case ELF::R_RISCV_TPREL_ADD:
     return true;
   }
   return false;

Original file line number	Diff line number	Diff line change
`@@ -820,6 +820,7 @@ static bool fixupGetsRelaxRelocation(const MCFixupKind Kind) {`
`820`	`820`	`case ELF::R_RISCV_TPREL_LO12_I:`
`821`	`821`	`case ELF::R_RISCV_TPREL_LO12_S:`
`822`	`822`	`case ELF::R_RISCV_TPREL_HI20:`
	`823`	`+ case ELF::R_RISCV_TPREL_ADD:`
`823`	`824`	`return true;`
`824`	`825`	`}`
`825`	`826`	`return false;`