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michaelmaitlandmichaelmaitland
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[RISCV] Split narrowing convert to FP pseudos by SEW
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6 files changed

+78
-55
lines changed

6 files changed

+78
-55
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td‎

Lines changed: 46 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -3762,36 +3762,45 @@ multiclass VPseudoVNCVTI_RM_W {
37623762
multiclass VPseudoVNCVTF_W_RM {
37633763
defvar constraint = "@earlyclobber $rd";
37643764
foreach m = MxListFW in {
3765-
defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m, constraint, TargetConstraintType=2>,
3766-
SchedUnary<"WriteVFNCvtIToFV", "ReadVFNCvtIToFV", m.MX,
3767-
forceMergeOpRead=true>;
3765+
foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in
3766+
defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m,
3767+
constraint, sew=e,
3768+
TargetConstraintType=2>,
3769+
SchedUnary<"WriteVFNCvtIToFV", "ReadVFNCvtIToFV", m.MX, e,
3770+
forceMergeOpRead=true>;
37683771
}
37693772
}
37703773

37713774
multiclass VPseudoVNCVTF_RM_W {
37723775
defvar constraint = "@earlyclobber $rd";
37733776
foreach m = MxListFW in {
3774-
defm _W : VPseudoConversionRM<m.vrclass, m.wvrclass, m, constraint>,
3775-
SchedUnary<"WriteVFNCvtIToFV", "ReadVFNCvtIToFV", m.MX,
3776-
forceMergeOpRead=true>;
3777+
foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in
3778+
defm _W : VPseudoConversionRM<m.vrclass, m.wvrclass, m, constraint, sew=e>,
3779+
SchedUnary<"WriteVFNCvtIToFV", "ReadVFNCvtIToFV", m.MX, e,
3780+
forceMergeOpRead=true>;
37773781
}
37783782
}
37793783

37803784
multiclass VPseudoVNCVTD_W {
37813785
defvar constraint = "@earlyclobber $rd";
37823786
foreach m = MxListFW in {
3783-
defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint, TargetConstraintType=2>,
3784-
SchedUnary<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV", m.MX,
3785-
forceMergeOpRead=true>;
3787+
foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in
3788+
defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint, sew=e,
3789+
TargetConstraintType=2>,
3790+
SchedUnary<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV", m.MX, e,
3791+
forceMergeOpRead=true>;
37863792
}
37873793
}
37883794

37893795
multiclass VPseudoVNCVTD_W_RM {
37903796
defvar constraint = "@earlyclobber $rd";
37913797
foreach m = MxListFW in {
3792-
defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m, constraint, TargetConstraintType=2>,
3793-
SchedUnary<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV", m.MX,
3794-
forceMergeOpRead=true>;
3798+
foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in
3799+
defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m,
3800+
constraint, sew=e,
3801+
TargetConstraintType=2>,
3802+
SchedUnary<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV", m.MX, e,
3803+
forceMergeOpRead=true>;
37953804
}
37963805
}
37973806

@@ -6027,52 +6036,59 @@ multiclass VPatConversionVI_WF_RM <string intrinsic, string instruction> {
60276036
}
60286037
}
60296038

6030-
multiclass VPatConversionVF_WI_RM <string intrinsic, string instruction> {
6039+
multiclass VPatConversionVF_WI_RM <string intrinsic, string instruction,
6040+
bit isSEWAware = 0> {
60316041
foreach fvtiToFWti = AllWidenableFloatVectors in {
60326042
defvar fvti = fvtiToFWti.Vti;
60336043
defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
60346044
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
60356045
GetVTypePredicates<iwti>.Predicates) in
60366046
defm : VPatConversionTARoundingMode<intrinsic, instruction, "W",
60376047
fvti.Vector, iwti.Vector, fvti.Mask, fvti.Log2SEW,
6038-
fvti.LMul, fvti.RegClass, iwti.RegClass>;
6048+
fvti.LMul, fvti.RegClass, iwti.RegClass,
6049+
isSEWAware>;
60396050
}
60406051
}
60416052

6042-
multiclass VPatConversionVF_WF <string intrinsic, string instruction> {
6053+
multiclass VPatConversionVF_WF<string intrinsic, string instruction,
6054+
bit isSEWAware = 0> {
60436055
foreach fvtiToFWti = AllWidenableFloatVectors in {
60446056
defvar fvti = fvtiToFWti.Vti;
60456057
defvar fwti = fvtiToFWti.Wti;
60466058
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
60476059
GetVTypePredicates<fwti>.Predicates) in
60486060
defm : VPatConversionTA<intrinsic, instruction, "W",
60496061
fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,
6050-
fvti.LMul, fvti.RegClass, fwti.RegClass>;
6062+
fvti.LMul, fvti.RegClass, fwti.RegClass, isSEWAware>;
60516063
}
60526064
}
60536065

6054-
multiclass VPatConversionVF_WF_RM <string intrinsic, string instruction,
6055-
list<VTypeInfoToWide> wlist = AllWidenableFloatVectors> {
6066+
multiclass VPatConversionVF_WF_RM<string intrinsic, string instruction,
6067+
list<VTypeInfoToWide> wlist = AllWidenableFloatVectors,
6068+
bit isSEWAware = 0> {
60566069
foreach fvtiToFWti = wlist in {
60576070
defvar fvti = fvtiToFWti.Vti;
60586071
defvar fwti = fvtiToFWti.Wti;
60596072
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
60606073
GetVTypePredicates<fwti>.Predicates) in
60616074
defm : VPatConversionTARoundingMode<intrinsic, instruction, "W",
60626075
fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,
6063-
fvti.LMul, fvti.RegClass, fwti.RegClass>;
6076+
fvti.LMul, fvti.RegClass, fwti.RegClass,
6077+
isSEWAware>;
60646078
}
60656079
}
60666080

6067-
multiclass VPatConversionVF_WF_BF_RM <string intrinsic, string instruction> {
6081+
multiclass VPatConversionVF_WF_BF_RM <string intrinsic, string instruction,
6082+
bit isSEWAware = 0> {
60686083
foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in {
60696084
defvar fvti = fvtiToFWti.Vti;
60706085
defvar fwti = fvtiToFWti.Wti;
60716086
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
60726087
GetVTypePredicates<fwti>.Predicates) in
60736088
defm : VPatConversionTARoundingMode<intrinsic, instruction, "W",
60746089
fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,
6075-
fvti.LMul, fvti.RegClass, fwti.RegClass>;
6090+
fvti.LMul, fvti.RegClass, fwti.RegClass,
6091+
isSEWAware>;
60766092
}
60776093
}
60786094

@@ -7320,21 +7336,24 @@ defm : VPatConversionVI_WF_RM<"int_riscv_vfncvt_xu_f_w", "PseudoVFNCVT_XU_F">;
73207336
defm : VPatConversionVI_WF_RM<"int_riscv_vfncvt_x_f_w", "PseudoVFNCVT_X_F">;
73217337
defm : VPatConversionVI_WF<"int_riscv_vfncvt_rtz_xu_f_w", "PseudoVFNCVT_RTZ_XU_F">;
73227338
defm : VPatConversionVI_WF<"int_riscv_vfncvt_rtz_x_f_w", "PseudoVFNCVT_RTZ_X_F">;
7323-
defm : VPatConversionVF_WI_RM <"int_riscv_vfncvt_f_xu_w", "PseudoVFNCVT_F_XU">;
7324-
defm : VPatConversionVF_WI_RM <"int_riscv_vfncvt_f_x_w", "PseudoVFNCVT_F_X">;
7339+
defm : VPatConversionVF_WI_RM<"int_riscv_vfncvt_f_xu_w", "PseudoVFNCVT_F_XU",
7340+
isSEWAware=1>;
7341+
defm : VPatConversionVF_WI_RM<"int_riscv_vfncvt_f_x_w", "PseudoVFNCVT_F_X",
7342+
isSEWAware=1>;
73257343
defvar WidenableFloatVectorsExceptF16 = !filter(fvtiToFWti, AllWidenableFloatVectors,
73267344
!ne(fvtiToFWti.Vti.Scalar, f16));
73277345
defm : VPatConversionVF_WF_RM<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F",
7328-
WidenableFloatVectorsExceptF16>;
7346+
WidenableFloatVectorsExceptF16, isSEWAware=1>;
73297347
// Define vfncvt.f.f.w for f16 when Zvfhmin is enable.
73307348
defvar F16WidenableFloatVectors = !filter(fvtiToFWti, AllWidenableFloatVectors,
73317349
!eq(fvtiToFWti.Vti.Scalar, f16));
73327350
let Predicates = [HasVInstructionsF16Minimal] in
73337351
defm : VPatConversionVF_WF_RM<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F",
7334-
F16WidenableFloatVectors>;
7352+
F16WidenableFloatVectors, isSEWAware=1>;
73357353
defm : VPatConversionVF_WF_BF_RM<"int_riscv_vfncvtbf16_f_f_w",
7336-
"PseudoVFNCVTBF16_F_F">;
7337-
defm : VPatConversionVF_WF<"int_riscv_vfncvt_rod_f_f_w", "PseudoVFNCVT_ROD_F_F">;
7354+
"PseudoVFNCVTBF16_F_F", isSEWAware=1>;
7355+
defm : VPatConversionVF_WF<"int_riscv_vfncvt_rod_f_f_w", "PseudoVFNCVT_ROD_F_F",
7356+
isSEWAware=1>;
73387357

73397358
//===----------------------------------------------------------------------===//
73407359
// 14. Vector Reduction Operations

‎llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -470,7 +470,7 @@ multiclass VPatNConvertI2FPSDNode_W_RM<SDPatternOperator vop,
470470
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
471471
GetVTypePredicates<iwti>.Predicates) in
472472
def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1))),
473-
(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
473+
(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_E"#fvti.SEW)
474474
(fvti.Vector (IMPLICIT_DEF)),
475475
iwti.RegClass:$rs1,
476476
// Value to indicate no rounding mode change in
@@ -1445,7 +1445,7 @@ foreach fvtiToFWti = AllWidenableFloatVectors in {
14451445
!listconcat(GetVTypePredicates<fvti>.Predicates,
14461446
GetVTypePredicates<fwti>.Predicates)) in
14471447
def : Pat<(fvti.Vector (fpround (fwti.Vector fwti.RegClass:$rs1))),
1448-
(!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX)
1448+
(!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX#"_E"#fvti.SEW)
14491449
(fvti.Vector (IMPLICIT_DEF)),
14501450
fwti.RegClass:$rs1,
14511451
// Value to indicate no rounding mode change in

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1389,7 +1389,7 @@ multiclass VPatNConvertI2FPVL_W_RM<SDPatternOperator vop,
13891389
def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1),
13901390
(iwti.Mask V0),
13911391
VLOpFrag)),
1392-
(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK")
1392+
(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")
13931393
(fvti.Vector (IMPLICIT_DEF)), iwti.RegClass:$rs1,
13941394
(iwti.Mask V0),
13951395
// Value to indicate no rounding mode change in
@@ -1408,7 +1408,7 @@ multiclass VPatNConvertI2FP_RM_VL_W<SDNode vop, string instruction_name> {
14081408
def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1),
14091409
(iwti.Mask V0), (XLenVT timm:$frm),
14101410
VLOpFrag)),
1411-
(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK")
1411+
(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")
14121412
(fvti.Vector (IMPLICIT_DEF)), iwti.RegClass:$rs1,
14131413
(iwti.Mask V0), timm:$frm, GPR:$vl, fvti.Log2SEW, TA_MA)>;
14141414
}
@@ -2703,7 +2703,7 @@ foreach fvtiToFWti = AllWidenableFloatVectors in {
27032703
def : Pat<(fvti.Vector (any_riscv_fpround_vl
27042704
(fwti.Vector fwti.RegClass:$rs1),
27052705
(fwti.Mask V0), VLOpFrag)),
2706-
(!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX#"_MASK")
2706+
(!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")
27072707
(fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1,
27082708
(fwti.Mask V0),
27092709
// Value to indicate no rounding mode change in
@@ -2716,7 +2716,7 @@ foreach fvtiToFWti = AllWidenableFloatVectors in {
27162716
def : Pat<(fvti.Vector (any_riscv_fncvt_rod_vl
27172717
(fwti.Vector fwti.RegClass:$rs1),
27182718
(fwti.Mask V0), VLOpFrag)),
2719-
(!cast<Instruction>("PseudoVFNCVT_ROD_F_F_W_"#fvti.LMul.MX#"_MASK")
2719+
(!cast<Instruction>("PseudoVFNCVT_ROD_F_F_W_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")
27202720
(fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1,
27212721
(fwti.Mask V0), GPR:$vl, fvti.Log2SEW, TA_MA)>;
27222722
}

‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td‎

Lines changed: 9 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -819,11 +819,13 @@ foreach mx = SchedMxListW in {
819819
}
820820
}
821821
foreach mx = SchedMxListFW in {
822-
defvar Cycles = SiFive7GetCyclesNarrowing<mx>.c;
823-
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListFW>.c;
824-
let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
825-
defm "" : LMULWriteResMX<"WriteVFNCvtIToFV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
826-
defm "" : LMULWriteResMX<"WriteVFNCvtFToFV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
822+
foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
823+
defvar Cycles = SiFive7GetCyclesNarrowing<mx>.c;
824+
defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
825+
let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
826+
defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtIToFV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
827+
defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtFToFV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
828+
}
827829
}
828830
}
829831

@@ -1182,9 +1184,9 @@ defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;
11821184
defm "" : LMULSEWReadAdvanceW<"ReadVFWCvtIToFV", 0>;
11831185
defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;
11841186
defm "" : LMULSEWReadAdvanceFW<"ReadVFWCvtFToFV", 0>;
1185-
defm "" : LMULReadAdvanceFW<"ReadVFNCvtIToFV", 0>;
1187+
defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtIToFV", 0>;
11861188
defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>;
1187-
defm "" : LMULReadAdvanceFW<"ReadVFNCvtFToFV", 0>;
1189+
defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtFToFV", 0>;
11881190

11891191
// 15. Vector Reduction Operations
11901192
def : ReadAdvance<ReadVIRedV, 0>;

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td‎

Lines changed: 9 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -563,11 +563,13 @@ foreach mx = SchedMxListW in {
563563
}
564564
}
565565
foreach mx = SchedMxListFW in {
566-
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
567-
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxListFW>.c;
568-
let Latency = 3, ReleaseAtCycles = [LMulLat] in {
569-
defm "" : LMULWriteResMX<"WriteVFNCvtIToFV", [SiFiveP600VectorArith], mx, IsWorstCase>;
570-
defm "" : LMULWriteResMX<"WriteVFNCvtFToFV", [SiFiveP600VectorArith], mx, IsWorstCase>;
566+
foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
567+
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
568+
defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
569+
let Latency = 3, ReleaseAtCycles = [LMulLat] in {
570+
defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtIToFV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
571+
defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtFToFV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
572+
}
571573
}
572574
}
573575

@@ -965,9 +967,9 @@ defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;
965967
defm "" : LMULSEWReadAdvanceW<"ReadVFWCvtIToFV", 0>;
966968
defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;
967969
defm "" : LMULSEWReadAdvanceFW<"ReadVFWCvtFToFV", 0>;
968-
defm "" : LMULReadAdvanceFW<"ReadVFNCvtIToFV", 0>;
970+
defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtIToFV", 0>;
969971
defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>;
970-
defm "" : LMULReadAdvanceFW<"ReadVFNCvtFToFV", 0>;
972+
defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtFToFV", 0>;
971973

972974
// 15. Vector Reduction Operations
973975
def : ReadAdvance<ReadVIRedV, 0>;

‎llvm/lib/Target/RISCV/RISCVScheduleV.td‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -468,9 +468,9 @@ defm "" : LMULSEWSchedWritesW<"WriteVFWCvtIToFV">;
468468
defm "" : LMULSchedWritesFW<"WriteVFWCvtFToIV">;
469469
defm "" : LMULSEWSchedWritesFW<"WriteVFWCvtFToFV">;
470470
// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
471-
defm "" : LMULSchedWritesFW<"WriteVFNCvtIToFV">;
471+
defm "" : LMULSEWSchedWritesFW<"WriteVFNCvtIToFV">;
472472
defm "" : LMULSchedWritesW<"WriteVFNCvtFToIV">;
473-
defm "" : LMULSchedWritesFW<"WriteVFNCvtFToFV">;
473+
defm "" : LMULSEWSchedWritesFW<"WriteVFNCvtFToFV">;
474474

475475
// 14. Vector Reduction Operations
476476
// The latency of reduction is determined by the size of the read resource.
@@ -694,9 +694,9 @@ defm "" : LMULSEWSchedReadsW<"ReadVFWCvtIToFV">;
694694
defm "" : LMULSchedReadsFW<"ReadVFWCvtFToIV">;
695695
defm "" : LMULSEWSchedReadsFW<"ReadVFWCvtFToFV">;
696696
// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
697-
defm "" : LMULSchedReadsFW<"ReadVFNCvtIToFV">;
697+
defm "" : LMULSEWSchedReadsFW<"ReadVFNCvtIToFV">;
698698
defm "" : LMULSchedReadsW<"ReadVFNCvtFToIV">;
699-
defm "" : LMULSchedReadsFW<"ReadVFNCvtFToFV">;
699+
defm "" : LMULSEWSchedReadsFW<"ReadVFNCvtFToFV">;
700700

701701
// 14. Vector Reduction Operations
702702
// 14.1. Vector Single-Width Integer Reduction Instructions
@@ -922,9 +922,9 @@ defm "" : LMULWriteRes<"WriteVFCvtFToIV", []>;
922922
defm "" : LMULSEWWriteResW<"WriteVFWCvtIToFV", []>;
923923
defm "" : LMULWriteResFW<"WriteVFWCvtFToIV", []>;
924924
defm "" : LMULSEWWriteResFW<"WriteVFWCvtFToFV", []>;
925-
defm "" : LMULWriteResFW<"WriteVFNCvtIToFV", []>;
925+
defm "" : LMULSEWWriteResFW<"WriteVFNCvtIToFV", []>;
926926
defm "" : LMULWriteResW<"WriteVFNCvtFToIV", []>;
927-
defm "" : LMULWriteResFW<"WriteVFNCvtFToFV", []>;
927+
defm "" : LMULSEWWriteResFW<"WriteVFNCvtFToFV", []>;
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// 14. Vector Reduction Operations
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defm "" : LMULSEWWriteRes<"WriteVIRedV_From", []>;
@@ -1079,9 +1079,9 @@ defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;
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defm "" : LMULSEWReadAdvanceW<"ReadVFWCvtIToFV", 0>;
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defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;
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defm "" : LMULSEWReadAdvanceFW<"ReadVFWCvtFToFV", 0>;
1082-
defm "" : LMULReadAdvanceFW<"ReadVFNCvtIToFV", 0>;
1082+
defm "" : LMULSEWReadAdvanceFW<"SEWReadVFNCvtIToFV", 0>;
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defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>;
1084-
defm "" : LMULReadAdvanceFW<"ReadVFNCvtFToFV", 0>;
1084+
defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtFToFV", 0>;
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// 14. Vector Reduction Operations
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def : ReadAdvance<ReadVIRedV, 0>;

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