Add a FIXME to remove the implementation in the future

wangpc-pp · wangpc-pp · commit 499752178968 · 2025-02-18T14:23:56.000+08:00
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -4337,6 +4337,7 @@ RISCVInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {
   return std::make_unique<RISCVPipelinerLoopInfo>(LHS, RHS, Cond);
 }
 
+// FIXME: We should remove this if we have a default generic scheduling model.
 bool RISCVInstrInfo::isHighLatencyDef(int Opc) const {
   unsigned RVVMCOpcode = RISCV::getRVVMCOpcode(Opc);
   Opc = RVVMCOpcode ? RVVMCOpcode : Opc;

Original file line number	Diff line number	Diff line change
`@@ -4337,6 +4337,7 @@ RISCVInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {`
`4337`	`4337`	`return std::make_unique<RISCVPipelinerLoopInfo>(LHS, RHS, Cond);`
`4338`	`4338`	`}`
`4339`	`4339`
	`4340`	`+// FIXME: We should remove this if we have a default generic scheduling model.`
`4340`	`4341`	`bool RISCVInstrInfo::isHighLatencyDef(int Opc) const {`
`4341`	`4342`	`unsigned RVVMCOpcode = RISCV::getRVVMCOpcode(Opc);`
`4342`	`4343`	`Opc = RVVMCOpcode ? RVVMCOpcode : Opc;`