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[AMDGPU][True16][MC] VOPC profile fake16 pseudo update (#113175)
Update VOPC profile with VOP3 pseudo: 1. On GFX11+, v_cmp_class_f16 has src1 type f16 for literals, however it's semantically interpreted as an integer. Update VOPC class f16 profile from operand type f16, i16 to f16, f16, currently updating it for fake16 format, and will update t16 format in the following patch. 2. 16bit V_CMP_CLASS instructions (V_CMP_**_U/I/F16) are named with `t16`, but actually using 32 bit registers. Correct it by updating the pseudo definitions with useRealTrue16/useFakeTrue16 predicates and rename these `t16` instructions to `fake16`. 3. Update the inst select so that `t16`/`fake16` instructions are selected in true16/fake16 flow. 4. The mir test file are impacted for a name change of these impacted 16 bit V_CMP instructions, but non-functional change to emitted code
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‎llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp‎

Lines changed: 57 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -1114,10 +1114,13 @@ static int getV_CMPOpcode(CmpInst::Predicate P, unsigned Size,
11141114
if (Size == 16 && !ST.has16BitInsts())
11151115
return -1;
11161116

1117-
const auto Select = [&](unsigned S16Opc, unsigned TrueS16Opc, unsigned S32Opc,
1117+
const auto Select = [&](unsigned S16Opc, unsigned TrueS16Opc,
1118+
unsigned FakeS16Opc, unsigned S32Opc,
11181119
unsigned S64Opc) {
11191120
if (Size == 16)
1120-
return ST.hasTrue16BitInsts() ? TrueS16Opc : S16Opc;
1121+
return ST.hasTrue16BitInsts()
1122+
? ST.useRealTrue16Insts() ? TrueS16Opc : FakeS16Opc
1123+
: S16Opc;
11211124
if (Size == 32)
11221125
return S32Opc;
11231126
return S64Opc;
@@ -1128,83 +1131,109 @@ static int getV_CMPOpcode(CmpInst::Predicate P, unsigned Size,
11281131
llvm_unreachable("Unknown condition code!");
11291132
case CmpInst::ICMP_NE:
11301133
return Select(AMDGPU::V_CMP_NE_U16_e64, AMDGPU::V_CMP_NE_U16_t16_e64,
1131-
AMDGPU::V_CMP_NE_U32_e64, AMDGPU::V_CMP_NE_U64_e64);
1134+
AMDGPU::V_CMP_NE_U16_fake16_e64, AMDGPU::V_CMP_NE_U32_e64,
1135+
AMDGPU::V_CMP_NE_U64_e64);
11321136
case CmpInst::ICMP_EQ:
11331137
return Select(AMDGPU::V_CMP_EQ_U16_e64, AMDGPU::V_CMP_EQ_U16_t16_e64,
1134-
AMDGPU::V_CMP_EQ_U32_e64, AMDGPU::V_CMP_EQ_U64_e64);
1138+
AMDGPU::V_CMP_EQ_U16_fake16_e64, AMDGPU::V_CMP_EQ_U32_e64,
1139+
AMDGPU::V_CMP_EQ_U64_e64);
11351140
case CmpInst::ICMP_SGT:
11361141
return Select(AMDGPU::V_CMP_GT_I16_e64, AMDGPU::V_CMP_GT_I16_t16_e64,
1137-
AMDGPU::V_CMP_GT_I32_e64, AMDGPU::V_CMP_GT_I64_e64);
1142+
AMDGPU::V_CMP_GT_I16_fake16_e64, AMDGPU::V_CMP_GT_I32_e64,
1143+
AMDGPU::V_CMP_GT_I64_e64);
11381144
case CmpInst::ICMP_SGE:
11391145
return Select(AMDGPU::V_CMP_GE_I16_e64, AMDGPU::V_CMP_GE_I16_t16_e64,
1140-
AMDGPU::V_CMP_GE_I32_e64, AMDGPU::V_CMP_GE_I64_e64);
1146+
AMDGPU::V_CMP_GE_I16_fake16_e64, AMDGPU::V_CMP_GE_I32_e64,
1147+
AMDGPU::V_CMP_GE_I64_e64);
11411148
case CmpInst::ICMP_SLT:
11421149
return Select(AMDGPU::V_CMP_LT_I16_e64, AMDGPU::V_CMP_LT_I16_t16_e64,
1143-
AMDGPU::V_CMP_LT_I32_e64, AMDGPU::V_CMP_LT_I64_e64);
1150+
AMDGPU::V_CMP_LT_I16_fake16_e64, AMDGPU::V_CMP_LT_I32_e64,
1151+
AMDGPU::V_CMP_LT_I64_e64);
11441152
case CmpInst::ICMP_SLE:
11451153
return Select(AMDGPU::V_CMP_LE_I16_e64, AMDGPU::V_CMP_LE_I16_t16_e64,
1146-
AMDGPU::V_CMP_LE_I32_e64, AMDGPU::V_CMP_LE_I64_e64);
1154+
AMDGPU::V_CMP_LE_I16_fake16_e64, AMDGPU::V_CMP_LE_I32_e64,
1155+
AMDGPU::V_CMP_LE_I64_e64);
11471156
case CmpInst::ICMP_UGT:
11481157
return Select(AMDGPU::V_CMP_GT_U16_e64, AMDGPU::V_CMP_GT_U16_t16_e64,
1149-
AMDGPU::V_CMP_GT_U32_e64, AMDGPU::V_CMP_GT_U64_e64);
1158+
AMDGPU::V_CMP_GT_U16_fake16_e64, AMDGPU::V_CMP_GT_U32_e64,
1159+
AMDGPU::V_CMP_GT_U64_e64);
11501160
case CmpInst::ICMP_UGE:
11511161
return Select(AMDGPU::V_CMP_GE_U16_e64, AMDGPU::V_CMP_GE_U16_t16_e64,
1152-
AMDGPU::V_CMP_GE_U32_e64, AMDGPU::V_CMP_GE_U64_e64);
1162+
AMDGPU::V_CMP_GE_U16_fake16_e64, AMDGPU::V_CMP_GE_U32_e64,
1163+
AMDGPU::V_CMP_GE_U64_e64);
11531164
case CmpInst::ICMP_ULT:
11541165
return Select(AMDGPU::V_CMP_LT_U16_e64, AMDGPU::V_CMP_LT_U16_t16_e64,
1155-
AMDGPU::V_CMP_LT_U32_e64, AMDGPU::V_CMP_LT_U64_e64);
1166+
AMDGPU::V_CMP_LT_U16_fake16_e64, AMDGPU::V_CMP_LT_U32_e64,
1167+
AMDGPU::V_CMP_LT_U64_e64);
11561168
case CmpInst::ICMP_ULE:
11571169
return Select(AMDGPU::V_CMP_LE_U16_e64, AMDGPU::V_CMP_LE_U16_t16_e64,
1158-
AMDGPU::V_CMP_LE_U32_e64, AMDGPU::V_CMP_LE_U64_e64);
1170+
AMDGPU::V_CMP_LE_U16_fake16_e64, AMDGPU::V_CMP_LE_U32_e64,
1171+
AMDGPU::V_CMP_LE_U64_e64);
11591172

11601173
case CmpInst::FCMP_OEQ:
11611174
return Select(AMDGPU::V_CMP_EQ_F16_e64, AMDGPU::V_CMP_EQ_F16_t16_e64,
1162-
AMDGPU::V_CMP_EQ_F32_e64, AMDGPU::V_CMP_EQ_F64_e64);
1175+
AMDGPU::V_CMP_EQ_F16_fake16_e64, AMDGPU::V_CMP_EQ_F32_e64,
1176+
AMDGPU::V_CMP_EQ_F64_e64);
11631177
case CmpInst::FCMP_OGT:
11641178
return Select(AMDGPU::V_CMP_GT_F16_e64, AMDGPU::V_CMP_GT_F16_t16_e64,
1165-
AMDGPU::V_CMP_GT_F32_e64, AMDGPU::V_CMP_GT_F64_e64);
1179+
AMDGPU::V_CMP_GT_F16_fake16_e64, AMDGPU::V_CMP_GT_F32_e64,
1180+
AMDGPU::V_CMP_GT_F64_e64);
11661181
case CmpInst::FCMP_OGE:
11671182
return Select(AMDGPU::V_CMP_GE_F16_e64, AMDGPU::V_CMP_GE_F16_t16_e64,
1168-
AMDGPU::V_CMP_GE_F32_e64, AMDGPU::V_CMP_GE_F64_e64);
1183+
AMDGPU::V_CMP_GE_F16_fake16_e64, AMDGPU::V_CMP_GE_F32_e64,
1184+
AMDGPU::V_CMP_GE_F64_e64);
11691185
case CmpInst::FCMP_OLT:
11701186
return Select(AMDGPU::V_CMP_LT_F16_e64, AMDGPU::V_CMP_LT_F16_t16_e64,
1171-
AMDGPU::V_CMP_LT_F32_e64, AMDGPU::V_CMP_LT_F64_e64);
1187+
AMDGPU::V_CMP_LT_F16_fake16_e64, AMDGPU::V_CMP_LT_F32_e64,
1188+
AMDGPU::V_CMP_LT_F64_e64);
11721189
case CmpInst::FCMP_OLE:
11731190
return Select(AMDGPU::V_CMP_LE_F16_e64, AMDGPU::V_CMP_LE_F16_t16_e64,
1174-
AMDGPU::V_CMP_LE_F32_e64, AMDGPU::V_CMP_LE_F64_e64);
1191+
AMDGPU::V_CMP_LE_F16_fake16_e64, AMDGPU::V_CMP_LE_F32_e64,
1192+
AMDGPU::V_CMP_LE_F64_e64);
11751193
case CmpInst::FCMP_ONE:
11761194
return Select(AMDGPU::V_CMP_NEQ_F16_e64, AMDGPU::V_CMP_NEQ_F16_t16_e64,
1177-
AMDGPU::V_CMP_NEQ_F32_e64, AMDGPU::V_CMP_NEQ_F64_e64);
1195+
AMDGPU::V_CMP_NEQ_F16_fake16_e64, AMDGPU::V_CMP_NEQ_F32_e64,
1196+
AMDGPU::V_CMP_NEQ_F64_e64);
11781197
case CmpInst::FCMP_ORD:
11791198
return Select(AMDGPU::V_CMP_O_F16_e64, AMDGPU::V_CMP_O_F16_t16_e64,
1180-
AMDGPU::V_CMP_O_F32_e64, AMDGPU::V_CMP_O_F64_e64);
1199+
AMDGPU::V_CMP_O_F16_fake16_e64, AMDGPU::V_CMP_O_F32_e64,
1200+
AMDGPU::V_CMP_O_F64_e64);
11811201
case CmpInst::FCMP_UNO:
11821202
return Select(AMDGPU::V_CMP_U_F16_e64, AMDGPU::V_CMP_U_F16_t16_e64,
1183-
AMDGPU::V_CMP_U_F32_e64, AMDGPU::V_CMP_U_F64_e64);
1203+
AMDGPU::V_CMP_U_F16_fake16_e64, AMDGPU::V_CMP_U_F32_e64,
1204+
AMDGPU::V_CMP_U_F64_e64);
11841205
case CmpInst::FCMP_UEQ:
11851206
return Select(AMDGPU::V_CMP_NLG_F16_e64, AMDGPU::V_CMP_NLG_F16_t16_e64,
1186-
AMDGPU::V_CMP_NLG_F32_e64, AMDGPU::V_CMP_NLG_F64_e64);
1207+
AMDGPU::V_CMP_NLG_F16_fake16_e64, AMDGPU::V_CMP_NLG_F32_e64,
1208+
AMDGPU::V_CMP_NLG_F64_e64);
11871209
case CmpInst::FCMP_UGT:
11881210
return Select(AMDGPU::V_CMP_NLE_F16_e64, AMDGPU::V_CMP_NLE_F16_t16_e64,
1189-
AMDGPU::V_CMP_NLE_F32_e64, AMDGPU::V_CMP_NLE_F64_e64);
1211+
AMDGPU::V_CMP_NLE_F16_fake16_e64, AMDGPU::V_CMP_NLE_F32_e64,
1212+
AMDGPU::V_CMP_NLE_F64_e64);
11901213
case CmpInst::FCMP_UGE:
11911214
return Select(AMDGPU::V_CMP_NLT_F16_e64, AMDGPU::V_CMP_NLT_F16_t16_e64,
1192-
AMDGPU::V_CMP_NLT_F32_e64, AMDGPU::V_CMP_NLT_F64_e64);
1215+
AMDGPU::V_CMP_NLT_F16_fake16_e64, AMDGPU::V_CMP_NLT_F32_e64,
1216+
AMDGPU::V_CMP_NLT_F64_e64);
11931217
case CmpInst::FCMP_ULT:
11941218
return Select(AMDGPU::V_CMP_NGE_F16_e64, AMDGPU::V_CMP_NGE_F16_t16_e64,
1195-
AMDGPU::V_CMP_NGE_F32_e64, AMDGPU::V_CMP_NGE_F64_e64);
1219+
AMDGPU::V_CMP_NGE_F16_fake16_e64, AMDGPU::V_CMP_NGE_F32_e64,
1220+
AMDGPU::V_CMP_NGE_F64_e64);
11961221
case CmpInst::FCMP_ULE:
11971222
return Select(AMDGPU::V_CMP_NGT_F16_e64, AMDGPU::V_CMP_NGT_F16_t16_e64,
1198-
AMDGPU::V_CMP_NGT_F32_e64, AMDGPU::V_CMP_NGT_F64_e64);
1223+
AMDGPU::V_CMP_NGT_F16_fake16_e64, AMDGPU::V_CMP_NGT_F32_e64,
1224+
AMDGPU::V_CMP_NGT_F64_e64);
11991225
case CmpInst::FCMP_UNE:
12001226
return Select(AMDGPU::V_CMP_NEQ_F16_e64, AMDGPU::V_CMP_NEQ_F16_t16_e64,
1201-
AMDGPU::V_CMP_NEQ_F32_e64, AMDGPU::V_CMP_NEQ_F64_e64);
1227+
AMDGPU::V_CMP_NEQ_F16_fake16_e64, AMDGPU::V_CMP_NEQ_F32_e64,
1228+
AMDGPU::V_CMP_NEQ_F64_e64);
12021229
case CmpInst::FCMP_TRUE:
12031230
return Select(AMDGPU::V_CMP_TRU_F16_e64, AMDGPU::V_CMP_TRU_F16_t16_e64,
1204-
AMDGPU::V_CMP_TRU_F32_e64, AMDGPU::V_CMP_TRU_F64_e64);
1231+
AMDGPU::V_CMP_TRU_F16_fake16_e64, AMDGPU::V_CMP_TRU_F32_e64,
1232+
AMDGPU::V_CMP_TRU_F64_e64);
12051233
case CmpInst::FCMP_FALSE:
12061234
return Select(AMDGPU::V_CMP_F_F16_e64, AMDGPU::V_CMP_F_F16_t16_e64,
1207-
AMDGPU::V_CMP_F_F32_e64, AMDGPU::V_CMP_F_F64_e64);
1235+
AMDGPU::V_CMP_F_F16_fake16_e64, AMDGPU::V_CMP_F_F32_e64,
1236+
AMDGPU::V_CMP_F_F64_e64);
12081237
}
12091238
}
12101239

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp‎

Lines changed: 68 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -5501,20 +5501,48 @@ unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const {
55015501
case AMDGPU::S_CMP_NLE_F32: return AMDGPU::V_CMP_NLE_F32_e64;
55025502
case AMDGPU::S_CMP_NEQ_F32: return AMDGPU::V_CMP_NEQ_F32_e64;
55035503
case AMDGPU::S_CMP_NLT_F32: return AMDGPU::V_CMP_NLT_F32_e64;
5504-
case AMDGPU::S_CMP_LT_F16: return AMDGPU::V_CMP_LT_F16_t16_e64;
5505-
case AMDGPU::S_CMP_EQ_F16: return AMDGPU::V_CMP_EQ_F16_t16_e64;
5506-
case AMDGPU::S_CMP_LE_F16: return AMDGPU::V_CMP_LE_F16_t16_e64;
5507-
case AMDGPU::S_CMP_GT_F16: return AMDGPU::V_CMP_GT_F16_t16_e64;
5508-
case AMDGPU::S_CMP_LG_F16: return AMDGPU::V_CMP_LG_F16_t16_e64;
5509-
case AMDGPU::S_CMP_GE_F16: return AMDGPU::V_CMP_GE_F16_t16_e64;
5510-
case AMDGPU::S_CMP_O_F16: return AMDGPU::V_CMP_O_F16_t16_e64;
5511-
case AMDGPU::S_CMP_U_F16: return AMDGPU::V_CMP_U_F16_t16_e64;
5512-
case AMDGPU::S_CMP_NGE_F16: return AMDGPU::V_CMP_NGE_F16_t16_e64;
5513-
case AMDGPU::S_CMP_NLG_F16: return AMDGPU::V_CMP_NLG_F16_t16_e64;
5514-
case AMDGPU::S_CMP_NGT_F16: return AMDGPU::V_CMP_NGT_F16_t16_e64;
5515-
case AMDGPU::S_CMP_NLE_F16: return AMDGPU::V_CMP_NLE_F16_t16_e64;
5516-
case AMDGPU::S_CMP_NEQ_F16: return AMDGPU::V_CMP_NEQ_F16_t16_e64;
5517-
case AMDGPU::S_CMP_NLT_F16: return AMDGPU::V_CMP_NLT_F16_t16_e64;
5504+
case AMDGPU::S_CMP_LT_F16:
5505+
return ST.useRealTrue16Insts() ? AMDGPU::V_CMP_LT_F16_t16_e64
5506+
: AMDGPU::V_CMP_LT_F16_fake16_e64;
5507+
case AMDGPU::S_CMP_EQ_F16:
5508+
return ST.useRealTrue16Insts() ? AMDGPU::V_CMP_EQ_F16_t16_e64
5509+
: AMDGPU::V_CMP_EQ_F16_fake16_e64;
5510+
case AMDGPU::S_CMP_LE_F16:
5511+
return ST.useRealTrue16Insts() ? AMDGPU::V_CMP_LE_F16_t16_e64
5512+
: AMDGPU::V_CMP_LE_F16_fake16_e64;
5513+
case AMDGPU::S_CMP_GT_F16:
5514+
return ST.useRealTrue16Insts() ? AMDGPU::V_CMP_GT_F16_t16_e64
5515+
: AMDGPU::V_CMP_GT_F16_fake16_e64;
5516+
case AMDGPU::S_CMP_LG_F16:
5517+
return ST.useRealTrue16Insts() ? AMDGPU::V_CMP_LG_F16_t16_e64
5518+
: AMDGPU::V_CMP_LG_F16_fake16_e64;
5519+
case AMDGPU::S_CMP_GE_F16:
5520+
return ST.useRealTrue16Insts() ? AMDGPU::V_CMP_GE_F16_t16_e64
5521+
: AMDGPU::V_CMP_GE_F16_fake16_e64;
5522+
case AMDGPU::S_CMP_O_F16:
5523+
return ST.useRealTrue16Insts() ? AMDGPU::V_CMP_O_F16_t16_e64
5524+
: AMDGPU::V_CMP_O_F16_fake16_e64;
5525+
case AMDGPU::S_CMP_U_F16:
5526+
return ST.useRealTrue16Insts() ? AMDGPU::V_CMP_U_F16_t16_e64
5527+
: AMDGPU::V_CMP_U_F16_fake16_e64;
5528+
case AMDGPU::S_CMP_NGE_F16:
5529+
return ST.useRealTrue16Insts() ? AMDGPU::V_CMP_NGE_F16_t16_e64
5530+
: AMDGPU::V_CMP_NGE_F16_fake16_e64;
5531+
case AMDGPU::S_CMP_NLG_F16:
5532+
return ST.useRealTrue16Insts() ? AMDGPU::V_CMP_NLG_F16_t16_e64
5533+
: AMDGPU::V_CMP_NLG_F16_fake16_e64;
5534+
case AMDGPU::S_CMP_NGT_F16:
5535+
return ST.useRealTrue16Insts() ? AMDGPU::V_CMP_NGT_F16_t16_e64
5536+
: AMDGPU::V_CMP_NGT_F16_fake16_e64;
5537+
case AMDGPU::S_CMP_NLE_F16:
5538+
return ST.useRealTrue16Insts() ? AMDGPU::V_CMP_NLE_F16_t16_e64
5539+
: AMDGPU::V_CMP_NLE_F16_fake16_e64;
5540+
case AMDGPU::S_CMP_NEQ_F16:
5541+
return ST.useRealTrue16Insts() ? AMDGPU::V_CMP_NEQ_F16_t16_e64
5542+
: AMDGPU::V_CMP_NEQ_F16_fake16_e64;
5543+
case AMDGPU::S_CMP_NLT_F16:
5544+
return ST.useRealTrue16Insts() ? AMDGPU::V_CMP_NLT_F16_t16_e64
5545+
: AMDGPU::V_CMP_NLT_F16_fake16_e64;
55185546
case AMDGPU::V_S_EXP_F32_e64: return AMDGPU::V_EXP_F32_e64;
55195547
case AMDGPU::V_S_EXP_F16_e64: return AMDGPU::V_EXP_F16_fake16_e64;
55205548
case AMDGPU::V_S_LOG_F32_e64: return AMDGPU::V_LOG_F32_e64;
@@ -7324,7 +7352,29 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
73247352
case AMDGPU::S_CMP_NGT_F32:
73257353
case AMDGPU::S_CMP_NLE_F32:
73267354
case AMDGPU::S_CMP_NEQ_F32:
7327-
case AMDGPU::S_CMP_NLT_F32:
7355+
case AMDGPU::S_CMP_NLT_F32: {
7356+
Register CondReg = MRI.createVirtualRegister(RI.getWaveMaskRegClass());
7357+
auto NewInstr =
7358+
BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(NewOpcode), CondReg)
7359+
.setMIFlags(Inst.getFlags());
7360+
if (AMDGPU::getNamedOperandIdx(NewOpcode, AMDGPU::OpName::src0_modifiers) >=
7361+
0) {
7362+
NewInstr
7363+
.addImm(0) // src0_modifiers
7364+
.add(Inst.getOperand(0)) // src0
7365+
.addImm(0) // src1_modifiers
7366+
.add(Inst.getOperand(1)) // src1
7367+
.addImm(0); // clamp
7368+
} else {
7369+
NewInstr.add(Inst.getOperand(0)).add(Inst.getOperand(1));
7370+
}
7371+
legalizeOperands(*NewInstr, MDT);
7372+
int SCCIdx = Inst.findRegisterDefOperandIdx(AMDGPU::SCC, /*TRI=*/nullptr);
7373+
MachineOperand SCCOp = Inst.getOperand(SCCIdx);
7374+
addSCCDefUsersToVALUWorklist(SCCOp, Inst, Worklist, CondReg);
7375+
Inst.eraseFromParent();
7376+
return;
7377+
}
73287378
case AMDGPU::S_CMP_LT_F16:
73297379
case AMDGPU::S_CMP_EQ_F16:
73307380
case AMDGPU::S_CMP_LE_F16:
@@ -7343,14 +7393,15 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
73437393
auto NewInstr =
73447394
BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(NewOpcode), CondReg)
73457395
.setMIFlags(Inst.getFlags());
7346-
if (AMDGPU::getNamedOperandIdx(NewOpcode,
7347-
AMDGPU::OpName::src0_modifiers) >= 0) {
7396+
if (AMDGPU::hasNamedOperand(NewOpcode, AMDGPU::OpName::src0_modifiers)) {
73487397
NewInstr
73497398
.addImm(0) // src0_modifiers
73507399
.add(Inst.getOperand(0)) // src0
73517400
.addImm(0) // src1_modifiers
73527401
.add(Inst.getOperand(1)) // src1
73537402
.addImm(0); // clamp
7403+
if (AMDGPU::hasNamedOperand(NewOpcode, AMDGPU::OpName::op_sel))
7404+
NewInstr.addImm(0); // op_sel0
73547405
} else {
73557406
NewInstr
73567407
.add(Inst.getOperand(0))

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