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Updated Patch, based on feedback.
1 parent d259fb1 commit 4f5dcb4

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2 files changed

+7
-7
lines changed

2 files changed

+7
-7
lines changed

llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1161,12 +1161,14 @@ void SIFoldOperandsImpl::foldOperand(
11611161

11621162
if (OpToFold.isImm())
11631163
UseMI->getOperand(1).ChangeToImmediate(OpToFold.getImm());
1164-
else if (OpToFold.isGlobal())
1164+
else if (OpToFold.isFI())
1165+
UseMI->getOperand(1).ChangeToFrameIndex(OpToFold.getIndex());
1166+
else {
1167+
assert(OpToFold.isGlobal());
11651168
UseMI->getOperand(1).ChangeToGA(OpToFold.getGlobal(),
11661169
OpToFold.getOffset(),
11671170
OpToFold.getTargetFlags());
1168-
else
1169-
UseMI->getOperand(1).ChangeToFrameIndex(OpToFold.getIndex());
1171+
}
11701172
UseMI->removeOperand(2); // Remove exec read (or src1 for readlane)
11711173
return;
11721174
}

llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2-
; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck %s
2+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck %s
33

44
define void @test_load_zext() {
55
; CHECK-LABEL: test_load_zext:
@@ -41,6 +41,4 @@ declare void @has_spgr_args(i32 inreg)
4141

4242
declare i32 @llvm.amdgcn.reloc.constant(metadata) #0
4343

44-
attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
45-
46-
!0 = !{!"DescriptorBuffer", i32 4, i32 8, i32 0, i32 0}
44+
!0 = !{!"DescriptorBuffer", i32 4, i32 8, i32 0, i32 0}

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