Added opt. Updated tests.

Author: egorshamshura

llvm/include/llvm/Analysis/ValueTracking.h

@@ -44,7 +44,7 @@ class TargetLibraryInfo;
 class IntrinsicInst;
 template <typename T> class ArrayRef;
 
-constexpr unsigned MaxAnalysisRecursionDepth = 6;
+constexpr unsigned MaxAnalysisRecursionDepth = 20;
 
 /// The max limit of the search depth in DecomposeGEPExpression() and
 /// getUnderlyingObject().

llvm/lib/Analysis/ValueTracking.cpp

@@ -71,6 +71,7 @@
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Compiler.h"
+#include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/KnownBits.h"
 #include "llvm/Support/KnownFPClass.h"
@@ -2367,9 +2368,29 @@ void computeKnownBits(const Value *V, const APInt &DemandedElts,
   }
 
   // Aligned pointers have trailing zeros - refine Known.Zero set
+  auto SameFunction = [](auto A, auto B) {
+    return A->getParent()->getParent() == B->getParent()->getParent();
+  };
   if (isa<PointerType>(V->getType())) {
     Align Alignment = V->getPointerAlignment(Q.DL);
     Known.Zero.setLowBits(Log2(Alignment));
+    for (auto *User : V->users()) {
+      if (auto *Load = dyn_cast<LoadInst>(User)) {
+        if (Q.CxtI && SameFunction(Load, Q.CxtI) &&
+            !isValidAssumeForContext(Load, Q.CxtI, Q.DT)) {
+          continue;
+        }
+        Known.Zero.setLowBits(Log2(Load->getAlign()));
+      }
+      if (auto *Store = dyn_cast<StoreInst>(User)) {
+        if (Store->getPointerOperand() != V ||
+            (Q.CxtI && SameFunction(Store, Q.CxtI) &&
+             !isValidAssumeForContext(Store, Q.CxtI, Q.DT))) {
+          continue;
+        }
+        Known.Zero.setLowBits(Log2(Store->getAlign()));
+      }
+    }
   }
 
   // computeKnownBitsFromContext strictly refines Known.

llvm/test/Analysis/ScalarEvolution/shift-recurrences.ll

@@ -558,11 +558,11 @@ define void @test_ashr_tc_either(i1 %a) {
 ; CHECK-NEXT:    %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
 ; CHECK-NEXT:    --> {0,+,1}<nuw><nsw><%loop> U: [0,61) S: [0,61) Exits: 60 LoopDispositions: { %loop: Computable }
 ; CHECK-NEXT:    %iv.ashr = phi i8 [ %start, %entry ], [ %iv.ashr.next, %loop ]
-; CHECK-NEXT:    --> %iv.ashr U: [-16,16) S: [-16,16) Exits: <<Unknown>> LoopDispositions: { %loop: Variant }
+; CHECK-NEXT:    --> %iv.ashr U: [-1,1) S: [-1,1) Exits: <<Unknown>> LoopDispositions: { %loop: Variant }
 ; CHECK-NEXT:    %iv.next = add i64 %iv, 1
 ; CHECK-NEXT:    --> {1,+,1}<nuw><nsw><%loop> U: [1,62) S: [1,62) Exits: 61 LoopDispositions: { %loop: Computable }
 ; CHECK-NEXT:    %iv.ashr.next = ashr i8 %iv.ashr, 1
-; CHECK-NEXT:    --> %iv.ashr.next U: [-16,16) S: [-16,16) Exits: <<Unknown>> LoopDispositions: { %loop: Variant }
+; CHECK-NEXT:    --> %iv.ashr.next U: [-1,1) S: [-1,1) Exits: <<Unknown>> LoopDispositions: { %loop: Variant }
 ; CHECK-NEXT:  Determining loop execution counts for: @test_ashr_tc_either
 ; CHECK-NEXT:  Loop %loop: backedge-taken count is i64 60
 ; CHECK-NEXT:  Loop %loop: constant max backedge-taken count is i64 60

llvm/test/Analysis/ValueTracking/monotonic-phi.ll

@@ -628,13 +628,10 @@ define i1 @test_ashr_zero_start(i8 %n) {
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
-; CHECK-NEXT:    [[A:%.*]] = phi i8 [ 0, [[ENTRY:%.*]] ], [ [[NEXT:%.*]], [[LOOP]] ]
-; CHECK-NEXT:    [[NEXT]] = ashr exact i8 [[A]], 1
-; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i8 [[A]], [[N:%.*]]
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i8 0, [[N:%.*]]
 ; CHECK-NEXT:    br i1 [[CMP1]], label [[EXIT:%.*]], label [[LOOP]]
 ; CHECK:       exit:
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i8 [[A]], 0
-; CHECK-NEXT:    ret i1 [[CMP]]
+; CHECK-NEXT:    ret i1 true
 ;
 entry:
   br label %loop

llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll

@@ -1327,43 +1327,36 @@ define amdgpu_ps void @load_uniform_P4_i16_b16_gfx12(ptr addrspace(4) inreg %ptr
 define amdgpu_ps void @load_uniform_P4_i16_b16_gfx11(ptr addrspace(4) inreg %ptra, ptr addrspace(4) inreg %ptrb, ptr addrspace(1) %out) {
 ; GFX7-LABEL: load_uniform_P4_i16_b16_gfx11:
 ; GFX7:       ; %bb.0:
-; GFX7-NEXT:    s_mov_b32 s2, -1
-; GFX7-NEXT:    s_mov_b32 s3, 0xf000
-; GFX7-NEXT:    buffer_load_ushort v2, off, s[0:3], 0
+; GFX7-NEXT:    s_load_dword s2, s[0:1], 0x0
 ; GFX7-NEXT:    s_load_dword s0, s[0:1], 0x0
-; GFX7-NEXT:    s_mov_b32 s2, 0
-; GFX7-NEXT:    s_waitcnt vmcnt(0)
-; GFX7-NEXT:    v_readfirstlane_b32 s1, v2
+; GFX7-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX7-NEXT:    s_add_i32 s0, s1, s0
+; GFX7-NEXT:    s_add_i32 s0, s2, s0
 ; GFX7-NEXT:    v_mov_b32_e32 v2, s0
+; GFX7-NEXT:    s_mov_b32 s2, 0
 ; GFX7-NEXT:    s_mov_b64 s[0:1], 0
 ; GFX7-NEXT:    buffer_store_short v2, v[0:1], s[0:3], 0 addr64
 ; GFX7-NEXT:    s_endpgm
 ;
 ; GFX11-True16-LABEL: load_uniform_P4_i16_b16_gfx11:
 ; GFX11-True16:       ; %bb.0:
-; GFX11-True16-NEXT:    v_mov_b32_e32 v2, 0
-; GFX11-True16-NEXT:    global_load_d16_b16 v2, v2, s[0:1]
+; GFX11-True16-NEXT:    s_clause 0x1
+; GFX11-True16-NEXT:    s_load_b32 s2, s[0:1], 0x0
 ; GFX11-True16-NEXT:    s_load_b32 s0, s[0:1], 0x0
-; GFX11-True16-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-True16-NEXT:    v_readfirstlane_b32 s1, v2
 ; GFX11-True16-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-True16-NEXT:    s_add_i32 s0, s1, s0
+; GFX11-True16-NEXT:    s_add_i32 s0, s2, s0
 ; GFX11-True16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11-True16-NEXT:    v_mov_b16_e32 v2.l, s0
 ; GFX11-True16-NEXT:    global_store_b16 v[0:1], v2, off
 ; GFX11-True16-NEXT:    s_endpgm
 ;
 ; GFX11-NoTrue16-LABEL: load_uniform_P4_i16_b16_gfx11:
 ; GFX11-NoTrue16:       ; %bb.0:
-; GFX11-NoTrue16-NEXT:    v_mov_b32_e32 v2, 0
-; GFX11-NoTrue16-NEXT:    global_load_u16 v2, v2, s[0:1]
+; GFX11-NoTrue16-NEXT:    s_clause 0x1
+; GFX11-NoTrue16-NEXT:    s_load_b32 s2, s[0:1], 0x0
 ; GFX11-NoTrue16-NEXT:    s_load_b32 s0, s[0:1], 0x0
-; GFX11-NoTrue16-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NoTrue16-NEXT:    v_readfirstlane_b32 s1, v2
 ; GFX11-NoTrue16-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NoTrue16-NEXT:    s_add_i32 s0, s1, s0
+; GFX11-NoTrue16-NEXT:    s_add_i32 s0, s2, s0
 ; GFX11-NoTrue16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11-NoTrue16-NEXT:    v_mov_b32_e32 v2, s0
 ; GFX11-NoTrue16-NEXT:    global_store_b16 v[0:1], v2, off
@@ -1488,43 +1481,36 @@ define amdgpu_ps void @load_uniform_P4_i16_anyextending_gfx12(ptr addrspace(4) i
 define amdgpu_ps void @load_uniform_P4_i16_anyextending_gfx11(ptr addrspace(4) inreg %ptra, ptr addrspace(4) inreg %ptrb, ptr addrspace(1) %out) {
 ; GFX7-LABEL: load_uniform_P4_i16_anyextending_gfx11:
 ; GFX7:       ; %bb.0:
-; GFX7-NEXT:    s_mov_b32 s2, -1
-; GFX7-NEXT:    s_mov_b32 s3, 0xf000
-; GFX7-NEXT:    buffer_load_ushort v2, off, s[0:3], 0
+; GFX7-NEXT:    s_load_dword s2, s[0:1], 0x0
 ; GFX7-NEXT:    s_load_dword s0, s[0:1], 0x0
-; GFX7-NEXT:    s_mov_b32 s2, 0
-; GFX7-NEXT:    s_waitcnt vmcnt(0)
-; GFX7-NEXT:    v_readfirstlane_b32 s1, v2
+; GFX7-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX7-NEXT:    s_add_i32 s0, s1, s0
+; GFX7-NEXT:    s_add_i32 s0, s2, s0
 ; GFX7-NEXT:    v_mov_b32_e32 v2, s0
+; GFX7-NEXT:    s_mov_b32 s2, 0
 ; GFX7-NEXT:    s_mov_b64 s[0:1], 0
 ; GFX7-NEXT:    buffer_store_short v2, v[0:1], s[0:3], 0 addr64
 ; GFX7-NEXT:    s_endpgm
 ;
 ; GFX11-True16-LABEL: load_uniform_P4_i16_anyextending_gfx11:
 ; GFX11-True16:       ; %bb.0:
-; GFX11-True16-NEXT:    v_mov_b32_e32 v2, 0
-; GFX11-True16-NEXT:    global_load_d16_b16 v2, v2, s[0:1]
+; GFX11-True16-NEXT:    s_clause 0x1
+; GFX11-True16-NEXT:    s_load_b32 s2, s[0:1], 0x0
 ; GFX11-True16-NEXT:    s_load_b32 s0, s[0:1], 0x0
-; GFX11-True16-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-True16-NEXT:    v_readfirstlane_b32 s1, v2
 ; GFX11-True16-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-True16-NEXT:    s_add_i32 s0, s1, s0
+; GFX11-True16-NEXT:    s_add_i32 s0, s2, s0
 ; GFX11-True16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11-True16-NEXT:    v_mov_b16_e32 v2.l, s0
 ; GFX11-True16-NEXT:    global_store_b16 v[0:1], v2, off
 ; GFX11-True16-NEXT:    s_endpgm
 ;
 ; GFX11-NoTrue16-LABEL: load_uniform_P4_i16_anyextending_gfx11:
 ; GFX11-NoTrue16:       ; %bb.0:
-; GFX11-NoTrue16-NEXT:    v_mov_b32_e32 v2, 0
-; GFX11-NoTrue16-NEXT:    global_load_u16 v2, v2, s[0:1]
+; GFX11-NoTrue16-NEXT:    s_clause 0x1
+; GFX11-NoTrue16-NEXT:    s_load_b32 s2, s[0:1], 0x0
 ; GFX11-NoTrue16-NEXT:    s_load_b32 s0, s[0:1], 0x0
-; GFX11-NoTrue16-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NoTrue16-NEXT:    v_readfirstlane_b32 s1, v2
 ; GFX11-NoTrue16-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NoTrue16-NEXT:    s_add_i32 s0, s1, s0
+; GFX11-NoTrue16-NEXT:    s_add_i32 s0, s2, s0
 ; GFX11-NoTrue16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11-NoTrue16-NEXT:    v_mov_b32_e32 v2, s0
 ; GFX11-NoTrue16-NEXT:    global_store_b16 v[0:1], v2, off

llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll

@@ -10,20 +10,17 @@ define amdgpu_kernel void @foo(ptr addrspace(5) %ptr5, ptr %p0, double %v0, <4 x
 ; CHECK-NEXT:    s_addc_u32 flat_scratch_hi, s13, 0
 ; CHECK-NEXT:    v_pk_mov_b32 v[46:47], 0, 0
 ; CHECK-NEXT:    flat_load_dword v42, v[46:47]
-; CHECK-NEXT:    s_mov_b64 s[34:35], s[8:9]
-; CHECK-NEXT:    s_load_dwordx4 s[64:67], s[34:35], 0x8
-; CHECK-NEXT:    s_load_dword s68, s[34:35], 0x0
+; CHECK-NEXT:    s_mov_b64 s[48:49], s[4:5]
+; CHECK-NEXT:    s_mov_b64 s[4:5], src_private_base
+; CHECK-NEXT:    s_load_dwordx4 s[64:67], s[8:9], 0x8
+; CHECK-NEXT:    s_load_dword s4, s[8:9], 0x0
 ; CHECK-NEXT:    s_add_u32 s0, s0, s17
 ; CHECK-NEXT:    s_addc_u32 s1, s1, 0
-; CHECK-NEXT:    s_mov_b64 s[8:9], src_private_base
-; CHECK-NEXT:    s_mov_b64 s[48:49], s[4:5]
+; CHECK-NEXT:    s_mov_b64 s[34:35], s[8:9]
+; CHECK-NEXT:    v_mov_b32_e32 v57, s5
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
-; CHECK-NEXT:    s_cmp_lg_u32 s68, -1
+; CHECK-NEXT:    v_mov_b32_e32 v56, s4
 ; CHECK-NEXT:    s_mov_b32 s4, 0
-; CHECK-NEXT:    s_cselect_b32 s5, s9, 0
-; CHECK-NEXT:    s_mov_b64 s[38:39], s[6:7]
-; CHECK-NEXT:    s_cselect_b32 s6, s68, 0
-; CHECK-NEXT:    v_mov_b32_e32 v57, s5
 ; CHECK-NEXT:    s_mov_b32 s5, s4
 ; CHECK-NEXT:    s_add_u32 s50, s34, 48
 ; CHECK-NEXT:    v_accvgpr_write_b32 a33, s5
@@ -34,10 +31,8 @@ define amdgpu_kernel void @foo(ptr addrspace(5) %ptr5, ptr %p0, double %v0, <4 x
 ; CHECK-NEXT:    s_addc_u32 s5, s5, G@gotpcrel32@hi+12
 ; CHECK-NEXT:    s_load_dwordx2 s[54:55], s[4:5], 0x0
 ; CHECK-NEXT:    s_mov_b32 s53, s14
-; CHECK-NEXT:    v_mov_b32_e32 v56, s6
 ; CHECK-NEXT:    v_pk_mov_b32 v[58:59], s[64:65], s[64:65] op_sel:[0,1]
 ; CHECK-NEXT:    s_mov_b64 s[4:5], s[48:49]
-; CHECK-NEXT:    s_mov_b64 s[6:7], s[38:39]
 ; CHECK-NEXT:    s_mov_b64 s[8:9], s[50:51]
 ; CHECK-NEXT:    s_mov_b32 s12, s14
 ; CHECK-NEXT:    s_mov_b32 s13, s15
@@ -47,6 +42,7 @@ define amdgpu_kernel void @foo(ptr addrspace(5) %ptr5, ptr %p0, double %v0, <4 x
 ; CHECK-NEXT:    s_mov_b32 s33, s16
 ; CHECK-NEXT:    s_mov_b32 s52, s15
 ; CHECK-NEXT:    s_mov_b64 s[36:37], s[10:11]
+; CHECK-NEXT:    s_mov_b64 s[38:39], s[6:7]
 ; CHECK-NEXT:    v_mov_b32_e32 v40, v0
 ; CHECK-NEXT:    v_mov_b32_e32 v62, s66
 ; CHECK-NEXT:    v_mov_b32_e32 v63, s67
@@ -72,14 +68,13 @@ define amdgpu_kernel void @foo(ptr addrspace(5) %ptr5, ptr %p0, double %v0, <4 x
 ; CHECK-NEXT:    s_swappc_b64 s[30:31], s[54:55]
 ; CHECK-NEXT:    flat_load_dwordx2 v[0:1], v[56:57] glc
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_mov_b32_e32 v1, s67
-; CHECK-NEXT:    v_mov_b32_e32 v0, s68
+; CHECK-NEXT:    v_mov_b32_e32 v0, s67
 ; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v42
 ; CHECK-NEXT:    flat_store_dwordx2 v[58:59], v[60:61]
 ; CHECK-NEXT:    s_waitcnt vmcnt(0)
 ; CHECK-NEXT:    flat_store_dwordx2 v[58:59], v[62:63]
-; CHECK-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
-; CHECK-NEXT:    buffer_store_dword v44, v0, s[0:3], 0 offen
+; CHECK-NEXT:    buffer_store_dword v0, v56, s[0:3], 0 offen offset:4
+; CHECK-NEXT:    buffer_store_dword v44, v56, s[0:3], 0 offen
 ; CHECK-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; CHECK-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; CHECK-NEXT:    s_cbranch_execz .LBB0_4