For gfx12.

Author: jwanggit86

llvm/lib/Target/AMDGPU/MIMGInstructions.td

@@ -500,7 +500,7 @@ class VIMAGE_NoSampler_gfx12<mimgopc op, string opcode,
                              string dns="">
   : VIMAGE_gfx12<op.GFX12, (outs DataRC:$vdata), num_addrs, dns> {
   let InOperandList = !con(AddrIns,
-                           (ins SReg_256_XNULL:$rsrc, DMask:$dmask, Dim:$dim,
+                           (ins SReg_RSRC:$rsrc, DMask:$dmask, Dim:$dim,
                                 CPol:$cpol, R128A16:$r128, A16:$a16, TFE:$tfe),
                            !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
   let AsmString = opcode#" $vdata, "#AddrAsm#", $rsrc$dmask$dim$cpol$r128$a16$tfe"
@@ -512,7 +512,7 @@ class VSAMPLE_Sampler_gfx12<mimgopc op, string opcode, RegisterClass DataRC,
                             string dns="">
   : VSAMPLE_gfx12<op.GFX12, (outs DataRC:$vdata), num_addrs, dns, Addr3RC> {
   let InOperandList = !con(AddrIns,
-                           (ins SReg_256_XNULL:$rsrc),
+                           (ins SReg_RSRC:$rsrc),
                            !if(BaseOpcode.Sampler, (ins SReg_128_XNULL:$samp), (ins)),
                            (ins DMask:$dmask, Dim:$dim, UNorm:$unorm,
                                 CPol:$cpol, R128A16:$r128, A16:$a16, TFE:$tfe,
@@ -529,7 +529,7 @@ class VSAMPLE_Sampler_nortn_gfx12<mimgopc op, string opcode,
                             string dns="">
   : VSAMPLE_gfx12<op.GFX12, (outs), num_addrs, dns, Addr3RC> {
   let InOperandList = !con(AddrIns,
-                           (ins SReg_256_XNULL:$rsrc),
+                           (ins SReg_RSRC:$rsrc),
                            !if(BaseOpcode.Sampler, (ins SReg_128_XNULL:$samp), (ins)),
                            (ins DMask:$dmask, Dim:$dim, UNorm:$unorm,
                                 CPol:$cpol, R128A16:$r128, A16:$a16, TFE:$tfe,
@@ -761,7 +761,7 @@ class VIMAGE_Store_gfx12<mimgopc op, string opcode,
   : VIMAGE_gfx12<op.GFX12, (outs), num_addrs, dns> {
   let InOperandList = !con((ins DataRC:$vdata),
                            AddrIns,
-                           (ins SReg_256_XNULL:$rsrc, DMask:$dmask, Dim:$dim,
+                           (ins SReg_RSRC:$rsrc, DMask:$dmask, Dim:$dim,
                                 CPol:$cpol, R128A16:$r128, A16:$a16, TFE:$tfe),
                            !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
   let AsmString = opcode#" $vdata, "#AddrAsm#", $rsrc$dmask$dim$cpol$r128$a16$tfe"
@@ -980,7 +980,7 @@ class VIMAGE_Atomic_gfx12<mimgopc op, string opcode, RegisterClass DataRC,
 
   let InOperandList = !con((ins DataRC:$vdata),
                            AddrIns,
-                           (ins SReg_256_XNULL:$rsrc, DMask:$dmask, Dim:$dim,
+                           (ins SReg_RSRC:$rsrc, DMask:$dmask, Dim:$dim,
                                  CPol:$cpol, R128A16:$r128, A16:$a16, TFE:$tfe));
   let AsmString = !if(!empty(renamed), opcode, renamed)#" $vdata, "#AddrAsm#
                   ", $rsrc$dmask$dim$cpol$r128$a16$tfe";

llvm/test/MC/AMDGPU/gfx12_asm_vimage.s

@@ -3,6 +3,9 @@
 image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
 // GFX12: encoding: [0x00,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
 
+image_load v[0:3], v0, s[0:3] dmask:0xf dim:SQ_RSRC_IMG_1D r128
+// GFX12: encoding: [0x10,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
 image_load v[1:4], [v2, v3], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D
 // GFX12: encoding: [0x01,0x00,0xc0,0xd3,0x01,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
 
@@ -287,6 +290,9 @@ image_load_mip_pck_sgn v5, [v0, v1], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_
 image_store v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
 // GFX12: encoding: [0x00,0x80,0xc1,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
 
+image_store v[0:3], v0, s[0:3] dmask:0xf dim:SQ_RSRC_IMG_1D r128
+// GFX12: encoding: [0x10,0x80,0xc1,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
 image_store v[1:4], [v2, v3], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D
 // GFX12: encoding: [0x01,0x80,0xc1,0xd3,0x01,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
 
@@ -495,6 +501,9 @@ image_store_mip_pck v5, [v0, v1], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STO
 image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
 // GFX12: encoding: [0x00,0x80,0x42,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
 
+image_atomic_swap v0, v0, s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_1D r128
+// GFX12: encoding: [0x10,0x80,0x42,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
 image_atomic_swap v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
 // GFX12: encoding: [0x01,0x80,0x42,0xd0,0x01,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
 
@@ -1075,6 +1084,9 @@ image_bvh8_intersect_ray v[0:9], [v[0:1], v[11:12], v[3:5], v[6:8], v9], s[0:3]
 image_get_resinfo v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D
 // GFX12: encoding: [0x00,0xc0,0x45,0xd0,0x04,0xc0,0x00,0x00,0x20,0x00,0x00,0x00]
 
+image_get_resinfo v4, v32, s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_1D r128
+// GFX12: encoding: [0x10,0xc0,0x45,0xd0,0x04,0xc0,0x00,0x00,0x20,0x00,0x00,0x00]
+
 image_get_resinfo v4, v32, s[96:103] dmask:0x2 dim:SQ_RSRC_IMG_2D
 // GFX12: encoding: [0x01,0xc0,0x85,0xd0,0x04,0xc0,0x00,0x00,0x20,0x00,0x00,0x00]