use 32-bit ops

Author: shiltian

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

@@ -5909,7 +5909,10 @@ bool AMDGPULegalizerInfo::legalizePointerAsRsrcIntrin(
 
   B.setInsertPt(B.getMBB(), ++B.getInsertPt());
 
+  auto ExtStride = B.buildAnyExt(S32, Stride);
+
   if (ST.has45BitNumRecordsBufferResource()) {
+    Register Zero = B.buildConstant(S32, 0).getReg(0);
     // Build the lower 64-bit value, which has a 57-bit base and the lower 7-bit
     // num_records.
     LLT PtrIntTy = LLT::scalar(MRI.getType(Pointer).getSizeInBits());
@@ -5921,13 +5924,15 @@ bool AMDGPULegalizerInfo::legalizePointerAsRsrcIntrin(
     // Build the higher 64-bit value, which has the higher 38-bit num_records,
     // 6-bit zero (omit), 16-bit stride and scale and 4-bit flag.
     auto NumRecordsRHS = B.buildLShr(S64, NumRecords, B.buildConstant(S32, 7));
-    auto ExtStride = B.buildAnyExt(S64, Stride);
-    auto ShiftedStride = B.buildShl(S64, ExtStride, B.buildConstant(S32, 44));
-    auto ExtFlags = B.buildAnyExt(S64, Flags);
-    auto NewFlags = B.buildAnd(S64, ExtFlags, B.buildConstant(S64, 0x3));
-    auto ShiftedFlags = B.buildShl(S64, NewFlags, B.buildConstant(S32, 60));
-    auto CombinedFields = B.buildOr(S64, NumRecordsRHS, ShiftedStride);
-    Register HighHalf = B.buildOr(S64, CombinedFields, ShiftedFlags).getReg(0);
+    auto ShiftedStride = B.buildShl(S32, ExtStride, B.buildConstant(S32, 12));
+    auto ExtShiftedStride =
+        B.buildMergeValues(S64, {Zero, ShiftedStride.getReg(0)});
+    auto ShiftedFlags = B.buildShl(S32, Flags, B.buildConstant(S32, 28));
+    auto ExtShiftedFlags =
+        B.buildMergeValues(S64, {Zero, ShiftedFlags.getReg(0)});
+    auto CombinedFields = B.buildOr(S64, NumRecordsRHS, ExtShiftedStride);
+    Register HighHalf =
+        B.buildOr(S64, CombinedFields, ExtShiftedFlags).getReg(0);
     B.buildMergeValues(Result, {LowHalf, HighHalf});
   } else {
     NumRecords = B.buildTrunc(S32, NumRecords).getReg(0);
@@ -5937,7 +5942,6 @@ bool AMDGPULegalizerInfo::legalizePointerAsRsrcIntrin(
 
     auto AndMask = B.buildConstant(S32, 0x0000ffff);
     auto Masked = B.buildAnd(S32, HighHalf, AndMask);
-    auto ExtStride = B.buildAnyExt(S32, Stride);
     auto ShiftConst = B.buildConstant(S32, 16);
     auto ShiftedStride = B.buildShl(S32, ExtStride, ShiftConst);
     auto NewHighHalf = B.buildOr(S32, Masked, ShiftedStride);

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

@@ -11602,9 +11602,11 @@ SDValue SITargetLowering::lowerPointerAsRsrcIntrin(SDNode *Op,
   SDValue NumRecords = Op->getOperand(3);
   SDValue Flags = Op->getOperand(4);
 
+  SDValue ExtStride = DAG.getAnyExtOrTrunc(Stride, Loc, MVT::i32);
   SDValue Rsrc;
 
   if (Subtarget->has45BitNumRecordsBufferResource()) {
+    SDValue Zero = DAG.getConstant(0, Loc, MVT::i32);
     // Build the lower 64-bit value, which has a 57-bit base and the lower 7-bit
     // num_records.
     SDValue ExtPointer = DAG.getAnyExtOrTrunc(Pointer, Loc, MVT::i64);
@@ -11619,20 +11621,24 @@ SDValue SITargetLowering::lowerPointerAsRsrcIntrin(SDNode *Op,
     SDValue NumRecordsRHS =
         DAG.getNode(ISD::SRL, Loc, MVT::i64, NumRecords,
                     DAG.getShiftAmountConstant(7, MVT::i32, Loc));
-    SDValue ExtStride = DAG.getAnyExtOrTrunc(Stride, Loc, MVT::i64);
     SDValue ShiftedStride =
-        DAG.getNode(ISD::SHL, Loc, MVT::i64, ExtStride,
-                    DAG.getShiftAmountConstant(44, MVT::i32, Loc));
-    SDValue ExtFlags = DAG.getAnyExtOrTrunc(Flags, Loc, MVT::i64);
-    SDValue NewFlags = DAG.getNode(ISD::AND, Loc, MVT::i64, ExtFlags,
-                                   DAG.getConstant(0x3, Loc, MVT::i64));
+        DAG.getNode(ISD::SHL, Loc, MVT::i32, ExtStride,
+                    DAG.getShiftAmountConstant(12, MVT::i32, Loc));
+    SDValue ExtShiftedStrideVec =
+        DAG.getNode(ISD::BUILD_VECTOR, Loc, MVT::v2i32, Zero, ShiftedStride);
+    SDValue ExtShiftedStride =
+        DAG.getNode(ISD::BITCAST, Loc, MVT::i64, ExtShiftedStrideVec);
     SDValue ShiftedFlags =
-        DAG.getNode(ISD::SHL, Loc, MVT::i64, NewFlags,
-                    DAG.getShiftAmountConstant(60, MVT::i32, Loc));
+        DAG.getNode(ISD::SHL, Loc, MVT::i32, Flags,
+                    DAG.getShiftAmountConstant(28, MVT::i32, Loc));
+    SDValue ExtShiftedFlagsVec =
+        DAG.getNode(ISD::BUILD_VECTOR, Loc, MVT::v2i32, Zero, ShiftedFlags);
+    SDValue ExtShiftedFlags =
+        DAG.getNode(ISD::BITCAST, Loc, MVT::i64, ExtShiftedFlagsVec);
     SDValue CombinedFields =
-        DAG.getNode(ISD::OR, Loc, MVT::i64, NumRecordsRHS, ShiftedStride);
+        DAG.getNode(ISD::OR, Loc, MVT::i64, NumRecordsRHS, ExtShiftedStride);
     SDValue HighHalf =
-        DAG.getNode(ISD::OR, Loc, MVT::i64, CombinedFields, ShiftedFlags);
+        DAG.getNode(ISD::OR, Loc, MVT::i64, CombinedFields, ExtShiftedFlags);
 
     Rsrc = DAG.getNode(ISD::BUILD_VECTOR, Loc, MVT::v2i64, LowHalf, HighHalf);
   } else {
@@ -11641,7 +11647,6 @@ SDValue SITargetLowering::lowerPointerAsRsrcIntrin(SDNode *Op,
         DAG.SplitScalar(Pointer, Loc, MVT::i32, MVT::i32);
     SDValue Mask = DAG.getConstant(0x0000ffff, Loc, MVT::i32);
     SDValue Masked = DAG.getNode(ISD::AND, Loc, MVT::i32, HighHalf, Mask);
-    SDValue ExtStride = DAG.getAnyExtOrTrunc(Stride, Loc, MVT::i32);
     SDValue ShiftedStride =
         DAG.getNode(ISD::SHL, Loc, MVT::i32, ExtStride,
                     DAG.getShiftAmountConstant(16, MVT::i32, Loc));