@@ -12501,13 +12501,13 @@ SDValue DAGCombiner::visitMHISTOGRAM(SDNode *N) {
1250112501 return SDValue();
1250212502}
1250312503
12504+ // Makes PARTIAL_REDUCE_*MLA(Acc, MUL(ZEXT(MulOpLHS), ZEXT(MulOpRHS)),
12505+ // Splat(1)) into
12506+ // PARTIAL_REDUCE_UMLA(Acc, MulOpLHS, MulOpRHS).
12507+ // Makes PARTIAL_REDUCE_*MLA(Acc, MUL(SEXT(MulOpLHS), SEXT(MulOpRHS)),
12508+ // Splat(1)) into
12509+ // PARTIAL_REDUCE_SMLA(Acc, MulOpLHS, MulOpRHS).
1250412510SDValue DAGCombiner::visitPARTIAL_REDUCE_MLA(SDNode *N) {
12505- // Makes PARTIAL_REDUCE_*MLA(Acc, MUL(ZEXT(MulOpLHS), ZEXT(MulOpRHS)),
12506- // Splat(1)) into
12507- // PARTIAL_REDUCE_UMLA(Acc, MulOpLHS, MulOpRHS).
12508- // Makes PARTIAL_REDUCE_*MLA(Acc, MUL(SEXT(MulOpLHS), SEXT(MulOpRHS)),
12509- // Splat(1)) into
12510- // PARTIAL_REDUCE_SMLA(Acc, MulOpLHS, MulOpRHS).
1251112511 SDLoc DL(N);
1251212512
1251312513 SDValue Op0 = N->getOperand(0);
@@ -12521,32 +12521,31 @@ SDValue DAGCombiner::visitPARTIAL_REDUCE_MLA(SDNode *N) {
1252112521 !ConstantOne.isOne())
1252212522 return SDValue();
1252312523
12524- SDValue ExtMulOpLHS = Op1->getOperand(0);
12525- SDValue ExtMulOpRHS = Op1->getOperand(1);
12526- unsigned ExtMulOpLHSOpcode = ExtMulOpLHS->getOpcode();
12527- unsigned ExtMulOpRHSOpcode = ExtMulOpRHS->getOpcode();
12528- if (!ISD::isExtOpcode(ExtMulOpLHSOpcode) ||
12529- !ISD::isExtOpcode(ExtMulOpRHSOpcode))
12524+ SDValue LHS = Op1->getOperand(0);
12525+ SDValue RHS = Op1->getOperand(1);
12526+ unsigned LHSOpcode = LHS->getOpcode();
12527+ unsigned RHSOpcode = RHS->getOpcode();
12528+ if (!ISD::isExtOpcode(LHSOpcode) || !ISD::isExtOpcode(RHSOpcode))
1253012529 return SDValue();
1253112530
12532- SDValue MulOpLHS = ExtMulOpLHS ->getOperand(0);
12533- SDValue MulOpRHS = ExtMulOpRHS ->getOperand(0);
12534- EVT MulOpLHSVT = MulOpLHS .getValueType();
12535- if (MulOpLHSVT != MulOpRHS .getValueType())
12531+ SDValue LHSExtOp = LHS ->getOperand(0);
12532+ SDValue RHSExtOp = RHS ->getOperand(0);
12533+ EVT LHSExtOpVT = LHSExtOp .getValueType();
12534+ if (LHSExtOpVT != RHSExtOp .getValueType())
1253612535 return SDValue();
1253712536
1253812537 // FIXME: Add a check to only perform the DAG combine if there is lowering
1253912538 // provided by the target
1254012539
12541- bool LHSIsSigned = ExtMulOpLHSOpcode == ISD::SIGN_EXTEND;
12542- bool RHSIsSigned = ExtMulOpRHSOpcode == ISD::SIGN_EXTEND;
12540+ bool LHSIsSigned = LHSOpcode == ISD::SIGN_EXTEND;
12541+ bool RHSIsSigned = RHSOpcode == ISD::SIGN_EXTEND;
1254312542 if (LHSIsSigned != RHSIsSigned)
1254412543 return SDValue();
1254512544
1254612545 unsigned NewOpcode =
1254712546 LHSIsSigned ? ISD::PARTIAL_REDUCE_SMLA : ISD::PARTIAL_REDUCE_UMLA;
12548- return DAG.getNode(NewOpcode, DL, N->getValueType(0), Op0, MulOpLHS ,
12549- MulOpRHS );
12547+ return DAG.getNode(NewOpcode, DL, N->getValueType(0), Op0, LHSExtOp ,
12548+ RHSExtOp );
1255012549}
1255112550
1255212551SDValue DAGCombiner::visitVP_STRIDED_LOAD(SDNode *N) {
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