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‎llvm/test/CodeGen/PowerPC/dmr-enable.ll‎

Lines changed: 242 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -129,6 +129,248 @@ entry:
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ret void
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}
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define void @text512(ptr %vp1, ptr %rp1, ptr %rp2, ptr %rp3, ptr %rp4) {
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; CHECK-LABEL: text512:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: dmsetdmrz dmr0
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; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
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; CHECK-NEXT: stxv v2, 16(r4)
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; CHECK-NEXT: stxv v3, 0(r4)
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; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
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; CHECK-NEXT: stxv v2, 16(r6)
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; CHECK-NEXT: stxv v3, 0(r6)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: text512:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: dmsetdmrz dmr0
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; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
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; CHECK-BE-NEXT: stxv v3, 16(r4)
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; CHECK-BE-NEXT: stxv v2, 0(r4)
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; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
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; CHECK-BE-NEXT: stxv v3, 16(r6)
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; CHECK-BE-NEXT: stxv v2, 0(r6)
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; CHECK-BE-NEXT: blr
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entry:
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%z = call <1024 x i1> @llvm.ppc.mma.dmsetdmrz()
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%x = call { <256 x i1>, <256 x i1> } @llvm.ppc.mma.dmxxextfdmr512(<1024 x i1> %z, i32 0)
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%p = extractvalue { <256 x i1>, <256 x i1 > } %x, 0
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store <256 x i1> %p, ptr %rp1, align 16
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%y = call { <256 x i1>, <256 x i1> } @llvm.ppc.mma.dmxxextfdmr512(<1024 x i1> %z, i32 1)
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%q = extractvalue { <256 x i1>, <256 x i1 > } %y, 0
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store <256 x i1> %q, ptr %rp3, align 16
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ret void
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}
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define void @text256(ptr %vp1, ptr %rp1, ptr %rp2, ptr %rp3, ptr %rp4) {
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; CHECK-LABEL: text256:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: dmsetdmrz dmr0
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; CHECK-NEXT: dmxxextfdmr256 vsp34, dmrrowp0, 0
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; CHECK-NEXT: stxv v2, 16(r4)
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; CHECK-NEXT: stxv v3, 0(r4)
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; CHECK-NEXT: dmxxextfdmr256 vsp34, dmrrowp1, 1
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; CHECK-NEXT: stxv v2, 16(r5)
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; CHECK-NEXT: stxv v3, 0(r5)
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; CHECK-NEXT: dmxxextfdmr256 vsp34, dmrrowp2, 2
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; CHECK-NEXT: stxv v2, 16(r6)
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; CHECK-NEXT: stxv v3, 0(r6)
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; CHECK-NEXT: dmxxextfdmr256 vsp34, dmrrowp3, 3
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; CHECK-NEXT: stxv v2, 16(r7)
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; CHECK-NEXT: stxv v3, 0(r7)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: text256:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: dmsetdmrz dmr0
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; CHECK-BE-NEXT: dmxxextfdmr256 vsp34, dmrrowp0, 0
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; CHECK-BE-NEXT: stxv v3, 16(r4)
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; CHECK-BE-NEXT: stxv v2, 0(r4)
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; CHECK-BE-NEXT: dmxxextfdmr256 vsp34, dmrrowp1, 1
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; CHECK-BE-NEXT: stxv v3, 16(r5)
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; CHECK-BE-NEXT: stxv v2, 0(r5)
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; CHECK-BE-NEXT: dmxxextfdmr256 vsp34, dmrrowp2, 2
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; CHECK-BE-NEXT: stxv v3, 16(r6)
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; CHECK-BE-NEXT: stxv v2, 0(r6)
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; CHECK-BE-NEXT: dmxxextfdmr256 vsp34, dmrrowp3, 3
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; CHECK-BE-NEXT: stxv v3, 16(r7)
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; CHECK-BE-NEXT: stxv v2, 0(r7)
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; CHECK-BE-NEXT: blr
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entry:
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%z = call <1024 x i1> @llvm.ppc.mma.dmsetdmrz()
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%x = call <256 x i1> @llvm.ppc.mma.dmxxextfdmr256(<1024 x i1> %z, i32 0)
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store <256 x i1> %x, ptr %rp1, align 16
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%q = call <256 x i1> @llvm.ppc.mma.dmxxextfdmr256(<1024 x i1> %z, i32 1)
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store <256 x i1> %q, ptr %rp2, align 16
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%w = call <256 x i1> @llvm.ppc.mma.dmxxextfdmr256(<1024 x i1> %z, i32 2)
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store <256 x i1> %w, ptr %rp3, align 16
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%y = call <256 x i1> @llvm.ppc.mma.dmxxextfdmr256(<1024 x i1> %z, i32 3)
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store <256 x i1> %y, ptr %rp4, align 16
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ret void
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}
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define void @tins512(ptr %vp1, ptr %vp2, ptr %vp3, ptr %vp4, ptr %rp1, ptr %rp2) {
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; CHECK-LABEL: tins512:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxv v2, 16(r3)
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; CHECK-NEXT: lxv v3, 0(r3)
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; CHECK-NEXT: lxv v4, 16(r4)
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; CHECK-NEXT: lxv v5, 0(r4)
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; CHECK-NEXT: dmsetdmrz dmr0
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; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp36, 0
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; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
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; CHECK-NEXT: stxvp vsp34, 96(r7)
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; CHECK-NEXT: stxvp vsp36, 64(r7)
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; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
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; CHECK-NEXT: stxvp vsp34, 32(r7)
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; CHECK-NEXT: stxvp vsp36, 0(r7)
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; CHECK-NEXT: lxv v2, 16(r5)
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; CHECK-NEXT: lxv v4, 16(r6)
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; CHECK-NEXT: lxv v3, 0(r5)
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; CHECK-NEXT: lxv v5, 0(r6)
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; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp34, vsp36, 1
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; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
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; CHECK-NEXT: stxvp vsp34, 96(r8)
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; CHECK-NEXT: stxvp vsp36, 64(r8)
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; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
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; CHECK-NEXT: stxvp vsp34, 32(r8)
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; CHECK-NEXT: stxvp vsp36, 0(r8)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: tins512:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: lxv v2, 0(r3)
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; CHECK-BE-NEXT: lxv v3, 16(r3)
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; CHECK-BE-NEXT: lxv v4, 0(r4)
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; CHECK-BE-NEXT: lxv v5, 16(r4)
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; CHECK-BE-NEXT: dmsetdmrz dmr0
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; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp36, 0
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; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
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; CHECK-BE-NEXT: stxvp vsp36, 96(r7)
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; CHECK-BE-NEXT: stxvp vsp34, 64(r7)
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; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
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; CHECK-BE-NEXT: stxvp vsp36, 32(r7)
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; CHECK-BE-NEXT: stxvp vsp34, 0(r7)
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; CHECK-BE-NEXT: lxv v2, 0(r5)
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; CHECK-BE-NEXT: lxv v4, 0(r6)
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; CHECK-BE-NEXT: lxv v3, 16(r5)
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; CHECK-BE-NEXT: lxv v5, 16(r6)
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; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp34, vsp36, 1
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; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
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; CHECK-BE-NEXT: stxvp vsp36, 96(r8)
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; CHECK-BE-NEXT: stxvp vsp34, 64(r8)
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; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
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; CHECK-BE-NEXT: stxvp vsp36, 32(r8)
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; CHECK-BE-NEXT: stxvp vsp34, 0(r8)
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; CHECK-BE-NEXT: blr
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entry:
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%z = call <1024 x i1> @llvm.ppc.mma.dmsetdmrz()
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%l1 = load <256 x i1>, ptr %vp1, align 16
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%r1 = load <256 x i1>, ptr %vp2, align 16
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%a = call <1024 x i1> @llvm.ppc.mma.dmxxinstdmr512(<1024 x i1> %z, <256 x i1> %l1, <256 x i1> %r1, i32 0)
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store <1024 x i1> %a, ptr %rp1, align 16
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%l2 = load <256 x i1>, ptr %vp3, align 16
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%r2 = load <256 x i1>, ptr %vp4, align 16
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%b = call <1024 x i1> @llvm.ppc.mma.dmxxinstdmr512(<1024 x i1> %a, <256 x i1> %l2, <256 x i1> %r2, i32 1)
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store <1024 x i1> %b, ptr %rp2, align 16
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ret void
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}
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define void @tins256(ptr %vp1, ptr %vp2, ptr %vp3, ptr %vp4, ptr %rp1, ptr %rp2, ptr %rp3, ptr %rp4) {
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; CHECK-LABEL: tins256:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxv v2, 16(r3)
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; CHECK-NEXT: lxv v3, 0(r3)
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; CHECK-NEXT: dmsetdmrz dmr0
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; CHECK-NEXT: dmxxinstdmr256 dmrrowp0, vsp34, 0
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; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
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; CHECK-NEXT: stxvp vsp34, 96(r7)
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; CHECK-NEXT: stxvp vsp36, 64(r7)
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; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
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; CHECK-NEXT: stxvp vsp34, 32(r7)
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; CHECK-NEXT: stxvp vsp36, 0(r7)
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; CHECK-NEXT: lxv v2, 16(r4)
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; CHECK-NEXT: lxv v3, 0(r4)
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; CHECK-NEXT: dmxxinstdmr256 dmrrowp1, vsp34, 1
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; CHECK-NEXT: dmxxextfdmr512 vsp36, vsp32, wacc0, 0
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; CHECK-NEXT: stxvp vsp36, 96(r8)
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; CHECK-NEXT: stxvp vsp32, 64(r8)
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; CHECK-NEXT: dmxxextfdmr512 vsp36, vsp32, wacc_hi0, 1
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; CHECK-NEXT: stxvp vsp36, 32(r8)
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; CHECK-NEXT: stxvp vsp32, 0(r8)
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; CHECK-NEXT: dmxxinstdmr256 dmrrowp2, vsp34, 2
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; CHECK-NEXT: dmxxextfdmr512 vsp36, vsp32, wacc0, 0
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; CHECK-NEXT: stxvp vsp36, 96(r9)
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; CHECK-NEXT: stxvp vsp32, 64(r9)
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; CHECK-NEXT: dmxxextfdmr512 vsp36, vsp32, wacc_hi0, 1
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; CHECK-NEXT: stxvp vsp36, 32(r9)
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; CHECK-NEXT: stxvp vsp32, 0(r9)
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; CHECK-NEXT: dmxxinstdmr256 dmrrowp3, vsp34, 3
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; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
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; CHECK-NEXT: stxvp vsp34, 96(r10)
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; CHECK-NEXT: stxvp vsp36, 64(r10)
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; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
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; CHECK-NEXT: stxvp vsp34, 32(r10)
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; CHECK-NEXT: stxvp vsp36, 0(r10)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: tins256:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: lxv v2, 0(r3)
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; CHECK-BE-NEXT: lxv v3, 16(r3)
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; CHECK-BE-NEXT: dmsetdmrz dmr0
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; CHECK-BE-NEXT: dmxxinstdmr256 dmrrowp0, vsp34, 0
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; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
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; CHECK-BE-NEXT: stxvp vsp36, 96(r7)
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; CHECK-BE-NEXT: stxvp vsp34, 64(r7)
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; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
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; CHECK-BE-NEXT: stxvp vsp36, 32(r7)
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; CHECK-BE-NEXT: stxvp vsp34, 0(r7)
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; CHECK-BE-NEXT: lxv v2, 0(r4)
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; CHECK-BE-NEXT: lxv v3, 16(r4)
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; CHECK-BE-NEXT: dmxxinstdmr256 dmrrowp1, vsp34, 1
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; CHECK-BE-NEXT: dmxxextfdmr512 vsp36, vsp32, wacc_hi0, 1
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; CHECK-BE-NEXT: stxvp vsp32, 96(r8)
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; CHECK-BE-NEXT: stxvp vsp36, 64(r8)
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; CHECK-BE-NEXT: dmxxextfdmr512 vsp36, vsp32, wacc0, 0
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; CHECK-BE-NEXT: stxvp vsp32, 32(r8)
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; CHECK-BE-NEXT: stxvp vsp36, 0(r8)
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; CHECK-BE-NEXT: dmxxinstdmr256 dmrrowp2, vsp34, 2
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; CHECK-BE-NEXT: dmxxextfdmr512 vsp36, vsp32, wacc_hi0, 1
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; CHECK-BE-NEXT: stxvp vsp32, 96(r9)
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; CHECK-BE-NEXT: stxvp vsp36, 64(r9)
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; CHECK-BE-NEXT: dmxxextfdmr512 vsp36, vsp32, wacc0, 0
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; CHECK-BE-NEXT: stxvp vsp32, 32(r9)
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; CHECK-BE-NEXT: stxvp vsp36, 0(r9)
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; CHECK-BE-NEXT: dmxxinstdmr256 dmrrowp3, vsp34, 3
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; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
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; CHECK-BE-NEXT: stxvp vsp36, 96(r10)
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; CHECK-BE-NEXT: stxvp vsp34, 64(r10)
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; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
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; CHECK-BE-NEXT: stxvp vsp36, 32(r10)
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; CHECK-BE-NEXT: stxvp vsp34, 0(r10)
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; CHECK-BE-NEXT: blr
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entry:
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%z = call <1024 x i1> @llvm.ppc.mma.dmsetdmrz()
355+
%l1 = load <256 x i1>, ptr %vp1, align 16
356+
%a = call <1024 x i1> @llvm.ppc.mma.dmxxinstdmr256(<1024 x i1> %z, <256 x i1> %l1, i32 0)
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store <1024 x i1> %a, ptr %rp1, align 16
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%l2 = load <256 x i1>, ptr %vp2, align 16
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%b = call <1024 x i1> @llvm.ppc.mma.dmxxinstdmr256(<1024 x i1> %a, <256 x i1> %l2, i32 1)
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store <1024 x i1> %b, ptr %rp2, align 16
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%l3 = load <256 x i1>, ptr %vp3, align 16
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%c = call <1024 x i1> @llvm.ppc.mma.dmxxinstdmr256(<1024 x i1> %b, <256 x i1> %l2, i32 2)
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store <1024 x i1> %c, ptr %rp3, align 16
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%l4 = load <256 x i1>, ptr %vp4, align 16
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%d = call <1024 x i1> @llvm.ppc.mma.dmxxinstdmr256(<1024 x i1> %c, <256 x i1> %l2, i32 3)
366+
store <1024 x i1> %d, ptr %rp4, align 16
367+
ret void
368+
}
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132370
declare <1024 x i1> @llvm.ppc.mma.dmsetdmrz()
133371
declare <1024 x i1> @llvm.ppc.mma.dmmr(<1024 x i1>)
134372
declare <1024 x i1> @llvm.ppc.mma.dmxor(<1024 x i1>, <1024 x i1>)
373+
declare <1024 x i1> @llvm.ppc.mma.dmxxinstdmr512(<1024 x i1>, <256 x i1>, <256 x i1>, i32)
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declare <1024 x i1> @llvm.ppc.mma.dmxxinstdmr256(<1024 x i1>, <256 x i1>, i32)
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declare { <256 x i1>, <256 x i1> } @llvm.ppc.mma.dmxxextfdmr512(<1024 x i1>, i32)
376+
declare <256 x i1> @llvm.ppc.mma.dmxxextfdmr256(<1024 x i1>, i32)

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