Unpack and zext instead of bitcast for v2s16

Author: gandhi56

llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp

@@ -501,11 +501,22 @@ void RegBankLegalizeHelper::lowerUnpackMinMax(MachineInstr &MI) {
 }
 
 void RegBankLegalizeHelper::lowerScalarizeV2S16(MachineInstr &MI) {
-  auto CastOp1 = B.buildBitcast(SgprRB_S32, MI.getOperand(1).getReg());
-  auto CastOp2 = B.buildBitcast(SgprRB_S32, MI.getOperand(2).getReg());
-  auto NewInstr =
-      B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {CastOp1, CastOp2});
-  B.buildBitcast({SgprRB, V2S16}, NewInstr.getReg(0));
+  auto Op1 = B.buildUnmerge({SgprRB, S16}, MI.getOperand(1).getReg());
+  auto Hi1 = Op1.getReg(0);
+  auto Lo1 = Op1.getReg(1);
+  auto Op2 = B.buildUnmerge({SgprRB, S16}, MI.getOperand(2).getReg());
+  auto Hi2 = Op2.getReg(0);
+  auto Lo2 = Op2.getReg(1);
+
+  auto CastHi1 = B.buildZExt(SgprRB_S32, Hi1);
+  auto CastLo1 = B.buildZExt(SgprRB_S32, Lo1);
+  auto CastHi2 = B.buildZExt(SgprRB_S32, Hi2);
+  auto CastLo2 = B.buildZExt(SgprRB_S32, Lo2);
+
+  auto ResHi = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {CastHi1, CastHi2});
+  auto ResLo = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {CastLo1, CastLo2});
+  
+  B.buildBuildVectorTrunc(MI.getOperand(0).getReg(), {ResHi.getReg(0), ResLo.getReg(0)});
   MI.eraseFromParent();
 }
 

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir

@@ -13,11 +13,16 @@ body: |
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
-    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY]](<2 x s16>)
-    ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY1]](<2 x s16>)
-    ; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[BITCAST]], [[BITCAST1]]
-    ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:sgpr(<2 x s16>) = G_BITCAST [[ADD]](s32)
-    ; CHECK-NEXT: S_ENDPGM 0, implicit %2:sgpr(<2 x s16>)
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:sgpr(s16), [[UV1:%[0-9]+]]:sgpr(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
+    ; CHECK-NEXT: [[UV2:%[0-9]+]]:sgpr(s16), [[UV3:%[0-9]+]]:sgpr(s16) = G_UNMERGE_VALUES [[COPY1]](<2 x s16>)
+    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[UV]](s16)
+    ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[UV1]](s16)
+    ; CHECK-NEXT: [[ZEXT2:%[0-9]+]]:sgpr(s32) = G_ZEXT [[UV2]](s16)
+    ; CHECK-NEXT: [[ZEXT3:%[0-9]+]]:sgpr(s32) = G_ZEXT [[UV3]](s16)
+    ; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[ZEXT]], [[ZEXT2]]
+    ; CHECK-NEXT: [[ADD1:%[0-9]+]]:sgpr(s32) = G_ADD [[ZEXT1]], [[ZEXT3]]
+    ; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ADD]](s32), [[ADD1]](s32)
+    ; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR_TRUNC]](<2 x s16>)
     %0:_(<2 x s16>) = COPY $sgpr0
     %1:_(<2 x s16>) = COPY $sgpr1
     %2:_(<2 x s16>) = G_ADD %0, %1

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.v2s16.mir

@@ -14,11 +14,16 @@ body: |
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
-    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY]](<2 x s16>)
-    ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY1]](<2 x s16>)
-    ; CHECK-NEXT: [[SUB:%[0-9]+]]:sgpr(s32) = G_SUB [[BITCAST]], [[BITCAST1]]
-    ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:sgpr(<2 x s16>) = G_BITCAST [[SUB]](s32)
-    ; CHECK-NEXT: S_ENDPGM 0, implicit %2:sgpr(<2 x s16>)
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:sgpr(s16), [[UV1:%[0-9]+]]:sgpr(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
+    ; CHECK-NEXT: [[UV2:%[0-9]+]]:sgpr(s16), [[UV3:%[0-9]+]]:sgpr(s16) = G_UNMERGE_VALUES [[COPY1]](<2 x s16>)
+    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[UV]](s16)
+    ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[UV1]](s16)
+    ; CHECK-NEXT: [[ZEXT2:%[0-9]+]]:sgpr(s32) = G_ZEXT [[UV2]](s16)
+    ; CHECK-NEXT: [[ZEXT3:%[0-9]+]]:sgpr(s32) = G_ZEXT [[UV3]](s16)
+    ; CHECK-NEXT: [[SUB:%[0-9]+]]:sgpr(s32) = G_SUB [[ZEXT]], [[ZEXT2]]
+    ; CHECK-NEXT: [[SUB1:%[0-9]+]]:sgpr(s32) = G_SUB [[ZEXT1]], [[ZEXT3]]
+    ; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[SUB]](s32), [[SUB1]](s32)
+    ; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR_TRUNC]](<2 x s16>)
     %0:_(<2 x s16>) = COPY $sgpr0
     %1:_(<2 x s16>) = COPY $sgpr1
     %2:_(<2 x s16>) = G_SUB %0, %1