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Update test file via update_llc_test_checks.py
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‎llvm/test/CodeGen/RISCV/zicond-fp-select-zfinx.ll‎

Lines changed: 239 additions & 103 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,16 @@
1-
; RUN: llc -mtriple=riscv64 -mattr=+zfinx,+zicond -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64ZFINX_ZICOND
2-
; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64ZFINX_NOZICOND
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
2+
; Zicond with zfinx(implies by zdinx)
33
; RUN: llc -mtriple=riscv64 -mattr=+zdinx,+zicond -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64ZDINX_ZICOND
44
; RUN: llc -mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64ZDINX_NOZICOND
5-
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64F
6-
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64D
75

6+
; Zicond with zfinx(implies by zhinx)
7+
; RUN: llc -mtriple=riscv64 -mattr=+zhinx,+zicond -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64ZHINX_ZICOND
8+
9+
; Baseline with classic FP registers (no *inx); zicond select should NOT trigger
10+
; RUN: llc -mtriple=riscv64 -mattr=+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64FD
11+
12+
; Check same optimize work on 32bit machine
813
; RUN: llc -mtriple=riscv32 -mattr=+zfinx,+zicond -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32ZFINX_ZICOND
9-
; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32ZFINX_NOZICOND
10-
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32F
1114

1215

1316
; This test checks that floating-point SELECT is lowered through integer
@@ -20,40 +23,57 @@
2023
; -----------------------------------------------------------------------------
2124

2225
define float @select_f32_i1(i1 %cond, float %t, float %f) nounwind {
23-
; RV64ZFINX_ZICOND-LABEL: select_f32_i1:
24-
; RV64ZFINX_ZICOND: czero
25-
; RV64ZFINX_ZICOND: czero
26-
; RV64ZFINX_ZICOND: or
27-
; RV64ZFINX_ZICOND-NOT: b{{(eq|ne)z?}}
28-
; RV64ZFINX_ZICOND: ret
29-
30-
; RV64ZFINX_NOZICOND-LABEL: select_f32_i1:
31-
; RV64ZFINX_NOZICOND: b{{(eq|ne)z?}}
32-
; RV64ZFINX_NOZICOND-NOT: czero.eqz
33-
; RV64ZFINX_NOZICOND-NOT: czero.nez
34-
35-
; RV64F-LABEL: select_f32_i1:
36-
; RV64F: b{{(eq|ne)z?}}
37-
; RV64F-NOT: czero.eqz
38-
; RV64F-NOT: czero.nez
39-
26+
; RV64ZDINX_ZICOND-LABEL: select_f32_i1:
27+
; RV64ZDINX_ZICOND: # %bb.0: # %entry
28+
; RV64ZDINX_ZICOND-NEXT: # kill: def $x12_w killed $x12_w def $x12
29+
; RV64ZDINX_ZICOND-NEXT: # kill: def $x11_w killed $x11_w def $x11
30+
; RV64ZDINX_ZICOND-NEXT: andi a0, a0, 1
31+
; RV64ZDINX_ZICOND-NEXT: czero.nez a2, a2, a0
32+
; RV64ZDINX_ZICOND-NEXT: czero.eqz a0, a1, a0
33+
; RV64ZDINX_ZICOND-NEXT: or a0, a0, a2
34+
; RV64ZDINX_ZICOND-NEXT: # kill: def $x10_w killed $x10_w killed $x10
35+
; RV64ZDINX_ZICOND-NEXT: ret
36+
;
37+
; RV64ZDINX_NOZICOND-LABEL: select_f32_i1:
38+
; RV64ZDINX_NOZICOND: # %bb.0: # %entry
39+
; RV64ZDINX_NOZICOND-NEXT: andi a3, a0, 1
40+
; RV64ZDINX_NOZICOND-NEXT: mv a0, a1
41+
; RV64ZDINX_NOZICOND-NEXT: bnez a3, .LBB0_2
42+
; RV64ZDINX_NOZICOND-NEXT: # %bb.1: # %entry
43+
; RV64ZDINX_NOZICOND-NEXT: mv a0, a2
44+
; RV64ZDINX_NOZICOND-NEXT: .LBB0_2: # %entry
45+
; RV64ZDINX_NOZICOND-NEXT: ret
46+
;
47+
; RV64ZHINX_ZICOND-LABEL: select_f32_i1:
48+
; RV64ZHINX_ZICOND: # %bb.0: # %entry
49+
; RV64ZHINX_ZICOND-NEXT: # kill: def $x12_w killed $x12_w def $x12
50+
; RV64ZHINX_ZICOND-NEXT: # kill: def $x11_w killed $x11_w def $x11
51+
; RV64ZHINX_ZICOND-NEXT: andi a0, a0, 1
52+
; RV64ZHINX_ZICOND-NEXT: czero.nez a2, a2, a0
53+
; RV64ZHINX_ZICOND-NEXT: czero.eqz a0, a1, a0
54+
; RV64ZHINX_ZICOND-NEXT: or a0, a0, a2
55+
; RV64ZHINX_ZICOND-NEXT: # kill: def $x10_w killed $x10_w killed $x10
56+
; RV64ZHINX_ZICOND-NEXT: ret
57+
;
58+
; RV64FD-LABEL: select_f32_i1:
59+
; RV64FD: # %bb.0: # %entry
60+
; RV64FD-NEXT: andi a0, a0, 1
61+
; RV64FD-NEXT: bnez a0, .LBB0_2
62+
; RV64FD-NEXT: # %bb.1: # %entry
63+
; RV64FD-NEXT: fmv.s fa0, fa1
64+
; RV64FD-NEXT: .LBB0_2: # %entry
65+
; RV64FD-NEXT: ret
66+
;
4067
; RV32ZFINX_ZICOND-LABEL: select_f32_i1:
41-
; RV32ZFINX_ZICOND: czero
42-
; RV32ZFINX_ZICOND: czero
43-
; RV32ZFINX_ZICOND: or
44-
; RV32ZFINX_ZICOND-NOT: b{{(eq|ne)z?}}
45-
; RV32ZFINX_ZICOND: ret
46-
47-
; RV32ZFINX_NOZICOND-LABEL: select_f32_i1:
48-
; RV32ZFINX_NOZICOND: b{{(eq|ne)z?}}
49-
; RV32ZFINX_NOZICOND-NOT: czero.eqz
50-
; RV32ZFINX_NOZICOND-NOT: czero.nez
51-
52-
; RV32F-LABEL: select_f32_i1:
53-
; RV32F: b{{(eq|ne)z?}}
54-
; RV32F-NOT: czero.eqz
55-
; RV32F-NOT: czero.nez
56-
68+
; RV32ZFINX_ZICOND: # %bb.0: # %entry
69+
; RV32ZFINX_ZICOND-NEXT: # kill: def $x12_w killed $x12_w def $x12
70+
; RV32ZFINX_ZICOND-NEXT: # kill: def $x11_w killed $x11_w def $x11
71+
; RV32ZFINX_ZICOND-NEXT: andi a0, a0, 1
72+
; RV32ZFINX_ZICOND-NEXT: czero.nez a2, a2, a0
73+
; RV32ZFINX_ZICOND-NEXT: czero.eqz a0, a1, a0
74+
; RV32ZFINX_ZICOND-NEXT: or a0, a0, a2
75+
; RV32ZFINX_ZICOND-NEXT: # kill: def $x10_w killed $x10_w killed $x10
76+
; RV32ZFINX_ZICOND-NEXT: ret
5777
entry:
5878
%sel = select i1 %cond, float %t, float %f
5979
ret float %sel
@@ -65,22 +85,50 @@ entry:
6585

6686
define double @select_f64_i1(i1 %cond, double %t, double %f) nounwind {
6787
; RV64ZDINX_ZICOND-LABEL: select_f64_i1:
68-
; RV64ZDINX_ZICOND: czero
69-
; RV64ZDINX_ZICOND: czero
70-
; RV64ZDINX_ZICOND: or
71-
; RV64ZDINX_ZICOND-NOT: b{{(eq|ne)z?}}
72-
; RV64ZDINX_ZICOND: ret
73-
88+
; RV64ZDINX_ZICOND: # %bb.0: # %entry
89+
; RV64ZDINX_ZICOND-NEXT: andi a0, a0, 1
90+
; RV64ZDINX_ZICOND-NEXT: czero.nez a2, a2, a0
91+
; RV64ZDINX_ZICOND-NEXT: czero.eqz a0, a1, a0
92+
; RV64ZDINX_ZICOND-NEXT: or a0, a0, a2
93+
; RV64ZDINX_ZICOND-NEXT: ret
94+
;
7495
; RV64ZDINX_NOZICOND-LABEL: select_f64_i1:
75-
; RV64ZDINX_NOZICOND: b{{(eq|ne)z?}}
76-
; RV64ZDINX_NOZICOND-NOT: czero.eqz
77-
; RV64ZDINX_NOZICOND-NOT: czero.nez
78-
79-
; RV64D-LABEL: select_f64_i1:
80-
; RV64D: b{{(eq|ne)z?}}
81-
; RV64D-NOT: czero.eqz
82-
; RV64D-NOT: czero.nez
83-
96+
; RV64ZDINX_NOZICOND: # %bb.0: # %entry
97+
; RV64ZDINX_NOZICOND-NEXT: andi a3, a0, 1
98+
; RV64ZDINX_NOZICOND-NEXT: mv a0, a1
99+
; RV64ZDINX_NOZICOND-NEXT: bnez a3, .LBB1_2
100+
; RV64ZDINX_NOZICOND-NEXT: # %bb.1: # %entry
101+
; RV64ZDINX_NOZICOND-NEXT: mv a0, a2
102+
; RV64ZDINX_NOZICOND-NEXT: .LBB1_2: # %entry
103+
; RV64ZDINX_NOZICOND-NEXT: ret
104+
;
105+
; RV64ZHINX_ZICOND-LABEL: select_f64_i1:
106+
; RV64ZHINX_ZICOND: # %bb.0: # %entry
107+
; RV64ZHINX_ZICOND-NEXT: andi a0, a0, 1
108+
; RV64ZHINX_ZICOND-NEXT: czero.nez a2, a2, a0
109+
; RV64ZHINX_ZICOND-NEXT: czero.eqz a0, a1, a0
110+
; RV64ZHINX_ZICOND-NEXT: or a0, a0, a2
111+
; RV64ZHINX_ZICOND-NEXT: ret
112+
;
113+
; RV64FD-LABEL: select_f64_i1:
114+
; RV64FD: # %bb.0: # %entry
115+
; RV64FD-NEXT: andi a0, a0, 1
116+
; RV64FD-NEXT: bnez a0, .LBB1_2
117+
; RV64FD-NEXT: # %bb.1: # %entry
118+
; RV64FD-NEXT: fmv.d fa0, fa1
119+
; RV64FD-NEXT: .LBB1_2: # %entry
120+
; RV64FD-NEXT: ret
121+
;
122+
; RV32ZFINX_ZICOND-LABEL: select_f64_i1:
123+
; RV32ZFINX_ZICOND: # %bb.0: # %entry
124+
; RV32ZFINX_ZICOND-NEXT: andi a0, a0, 1
125+
; RV32ZFINX_ZICOND-NEXT: czero.nez a3, a3, a0
126+
; RV32ZFINX_ZICOND-NEXT: czero.eqz a1, a1, a0
127+
; RV32ZFINX_ZICOND-NEXT: czero.nez a4, a4, a0
128+
; RV32ZFINX_ZICOND-NEXT: czero.eqz a2, a2, a0
129+
; RV32ZFINX_ZICOND-NEXT: or a0, a1, a3
130+
; RV32ZFINX_ZICOND-NEXT: or a1, a2, a4
131+
; RV32ZFINX_ZICOND-NEXT: ret
84132
entry:
85133
%sel = select i1 %cond, double %t, double %f
86134
ret double %sel
@@ -92,22 +140,79 @@ entry:
92140

93141
define double @select_f64_fcmp(double %a, double %b, double %c, double %d) nounwind {
94142
; RV64ZDINX_ZICOND-LABEL: select_f64_fcmp:
95-
; RV64ZDINX_ZICOND: czero
96-
; RV64ZDINX_ZICOND: czero
97-
; RV64ZDINX_ZICOND: or
98-
; RV64ZDINX_ZICOND-NOT: b{{(eq|ne)z?}}
99-
; RV64ZDINX_ZICOND: ret
100-
143+
; RV64ZDINX_ZICOND: # %bb.0: # %entry
144+
; RV64ZDINX_ZICOND-NEXT: flt.d a0, a1, a0
145+
; RV64ZDINX_ZICOND-NEXT: czero.nez a1, a3, a0
146+
; RV64ZDINX_ZICOND-NEXT: czero.eqz a0, a2, a0
147+
; RV64ZDINX_ZICOND-NEXT: or a0, a0, a1
148+
; RV64ZDINX_ZICOND-NEXT: ret
149+
;
101150
; RV64ZDINX_NOZICOND-LABEL: select_f64_fcmp:
102-
; RV64ZDINX_NOZICOND: b{{(eq|ne)z?}}
103-
; RV64ZDINX_NOZICOND-NOT: czero.eqz
104-
; RV64ZDINX_NOZICOND-NOT: czero.nez
105-
106-
; RV64D-LABEL: select_f64_fcmp:
107-
; RV64D: b{{(eq|ne)z?}}
108-
; RV64D-NOT: czero.eqz
109-
; RV64D-NOT: czero.nez
110-
151+
; RV64ZDINX_NOZICOND: # %bb.0: # %entry
152+
; RV64ZDINX_NOZICOND-NEXT: flt.d a1, a1, a0
153+
; RV64ZDINX_NOZICOND-NEXT: mv a0, a2
154+
; RV64ZDINX_NOZICOND-NEXT: bnez a1, .LBB2_2
155+
; RV64ZDINX_NOZICOND-NEXT: # %bb.1: # %entry
156+
; RV64ZDINX_NOZICOND-NEXT: mv a0, a3
157+
; RV64ZDINX_NOZICOND-NEXT: .LBB2_2: # %entry
158+
; RV64ZDINX_NOZICOND-NEXT: ret
159+
;
160+
; RV64ZHINX_ZICOND-LABEL: select_f64_fcmp:
161+
; RV64ZHINX_ZICOND: # %bb.0: # %entry
162+
; RV64ZHINX_ZICOND-NEXT: addi sp, sp, -32
163+
; RV64ZHINX_ZICOND-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
164+
; RV64ZHINX_ZICOND-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
165+
; RV64ZHINX_ZICOND-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
166+
; RV64ZHINX_ZICOND-NEXT: mv s0, a3
167+
; RV64ZHINX_ZICOND-NEXT: mv s1, a2
168+
; RV64ZHINX_ZICOND-NEXT: call __gtdf2
169+
; RV64ZHINX_ZICOND-NEXT: sgtz a0, a0
170+
; RV64ZHINX_ZICOND-NEXT: czero.nez a1, s0, a0
171+
; RV64ZHINX_ZICOND-NEXT: czero.eqz a0, s1, a0
172+
; RV64ZHINX_ZICOND-NEXT: or a0, a0, a1
173+
; RV64ZHINX_ZICOND-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
174+
; RV64ZHINX_ZICOND-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
175+
; RV64ZHINX_ZICOND-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
176+
; RV64ZHINX_ZICOND-NEXT: addi sp, sp, 32
177+
; RV64ZHINX_ZICOND-NEXT: ret
178+
;
179+
; RV64FD-LABEL: select_f64_fcmp:
180+
; RV64FD: # %bb.0: # %entry
181+
; RV64FD-NEXT: flt.d a0, fa1, fa0
182+
; RV64FD-NEXT: fmv.d fa0, fa2
183+
; RV64FD-NEXT: bnez a0, .LBB2_2
184+
; RV64FD-NEXT: # %bb.1: # %entry
185+
; RV64FD-NEXT: fmv.d fa0, fa3
186+
; RV64FD-NEXT: .LBB2_2: # %entry
187+
; RV64FD-NEXT: ret
188+
;
189+
; RV32ZFINX_ZICOND-LABEL: select_f64_fcmp:
190+
; RV32ZFINX_ZICOND: # %bb.0: # %entry
191+
; RV32ZFINX_ZICOND-NEXT: addi sp, sp, -32
192+
; RV32ZFINX_ZICOND-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
193+
; RV32ZFINX_ZICOND-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
194+
; RV32ZFINX_ZICOND-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
195+
; RV32ZFINX_ZICOND-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
196+
; RV32ZFINX_ZICOND-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
197+
; RV32ZFINX_ZICOND-NEXT: mv s0, a7
198+
; RV32ZFINX_ZICOND-NEXT: mv s1, a6
199+
; RV32ZFINX_ZICOND-NEXT: mv s2, a5
200+
; RV32ZFINX_ZICOND-NEXT: mv s3, a4
201+
; RV32ZFINX_ZICOND-NEXT: call __gtdf2
202+
; RV32ZFINX_ZICOND-NEXT: sgtz a0, a0
203+
; RV32ZFINX_ZICOND-NEXT: czero.nez a1, s1, a0
204+
; RV32ZFINX_ZICOND-NEXT: czero.eqz a2, s3, a0
205+
; RV32ZFINX_ZICOND-NEXT: czero.nez a3, s0, a0
206+
; RV32ZFINX_ZICOND-NEXT: czero.eqz a4, s2, a0
207+
; RV32ZFINX_ZICOND-NEXT: or a0, a2, a1
208+
; RV32ZFINX_ZICOND-NEXT: or a1, a4, a3
209+
; RV32ZFINX_ZICOND-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
210+
; RV32ZFINX_ZICOND-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
211+
; RV32ZFINX_ZICOND-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
212+
; RV32ZFINX_ZICOND-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
213+
; RV32ZFINX_ZICOND-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
214+
; RV32ZFINX_ZICOND-NEXT: addi sp, sp, 32
215+
; RV32ZFINX_ZICOND-NEXT: ret
111216
entry:
112217
%cmp = fcmp ogt double %a, %b
113218
%sel = select i1 %cmp, double %c, double %d
@@ -119,41 +224,72 @@ entry:
119224
; -----------------------------------------------------------------------------
120225

121226
define dso_local noundef half @select_half_i1(i1 %cond, half %a, half %b) nounwind {
122-
; RV64ZFINX_ZICOND-LABEL: select_half_i1:
123-
; RV64ZFINX_ZICOND: czero
124-
; RV64ZFINX_ZICOND: czero
125-
; RV64ZFINX_ZICOND: or
126-
; RV64ZFINX_ZICOND-NOT: b{{(eq|ne)z?}}
127-
; RV64ZFINX_ZICOND: ret
128-
129-
; RV64ZFINX_NOZICOND-LABEL: select_half_i1:
130-
; RV64ZFINX_NOZICOND: b{{(eq|ne)z?}}
131-
; RV64ZFINX_NOZICOND-NOT: czero.eqz
132-
; RV64ZFINX_NOZICOND-NOT: czero.nez
133-
134-
; RV64F-LABEL: select_half_i1:
135-
; RV64F: b{{(eq|ne)z?}}
136-
; RV64F-NOT: czero.eqz
137-
; RV64F-NOT: czero.nez
138-
227+
; RV64ZDINX_ZICOND-LABEL: select_half_i1:
228+
; RV64ZDINX_ZICOND: # %bb.0: # %entry
229+
; RV64ZDINX_ZICOND-NEXT: # kill: def $x12_w killed $x12_w def $x12
230+
; RV64ZDINX_ZICOND-NEXT: # kill: def $x11_w killed $x11_w def $x11
231+
; RV64ZDINX_ZICOND-NEXT: andi a0, a0, 1
232+
; RV64ZDINX_ZICOND-NEXT: czero.nez a2, a2, a0
233+
; RV64ZDINX_ZICOND-NEXT: czero.eqz a0, a1, a0
234+
; RV64ZDINX_ZICOND-NEXT: or a0, a0, a2
235+
; RV64ZDINX_ZICOND-NEXT: lui a1, 1048560
236+
; RV64ZDINX_ZICOND-NEXT: or a0, a0, a1
237+
; RV64ZDINX_ZICOND-NEXT: # kill: def $x10_w killed $x10_w killed $x10
238+
; RV64ZDINX_ZICOND-NEXT: ret
239+
;
240+
; RV64ZDINX_NOZICOND-LABEL: select_half_i1:
241+
; RV64ZDINX_NOZICOND: # %bb.0: # %entry
242+
; RV64ZDINX_NOZICOND-NEXT: # kill: def $x12_w killed $x12_w def $x12
243+
; RV64ZDINX_NOZICOND-NEXT: andi a0, a0, 1
244+
; RV64ZDINX_NOZICOND-NEXT: # kill: def $x11_w killed $x11_w def $x11
245+
; RV64ZDINX_NOZICOND-NEXT: bnez a0, .LBB3_2
246+
; RV64ZDINX_NOZICOND-NEXT: # %bb.1: # %entry
247+
; RV64ZDINX_NOZICOND-NEXT: mv a1, a2
248+
; RV64ZDINX_NOZICOND-NEXT: .LBB3_2: # %entry
249+
; RV64ZDINX_NOZICOND-NEXT: lui a0, 1048560
250+
; RV64ZDINX_NOZICOND-NEXT: or a0, a1, a0
251+
; RV64ZDINX_NOZICOND-NEXT: # kill: def $x10_w killed $x10_w killed $x10
252+
; RV64ZDINX_NOZICOND-NEXT: ret
253+
;
254+
; RV64ZHINX_ZICOND-LABEL: select_half_i1:
255+
; RV64ZHINX_ZICOND: # %bb.0: # %entry
256+
; RV64ZHINX_ZICOND-NEXT: # kill: def $x12_h killed $x12_h def $x12
257+
; RV64ZHINX_ZICOND-NEXT: # kill: def $x11_h killed $x11_h def $x11
258+
; RV64ZHINX_ZICOND-NEXT: andi a0, a0, 1
259+
; RV64ZHINX_ZICOND-NEXT: czero.nez a2, a2, a0
260+
; RV64ZHINX_ZICOND-NEXT: czero.eqz a0, a1, a0
261+
; RV64ZHINX_ZICOND-NEXT: or a0, a0, a2
262+
; RV64ZHINX_ZICOND-NEXT: # kill: def $x10_h killed $x10_h killed $x10
263+
; RV64ZHINX_ZICOND-NEXT: ret
264+
;
265+
; RV64FD-LABEL: select_half_i1:
266+
; RV64FD: # %bb.0: # %entry
267+
; RV64FD-NEXT: andi a0, a0, 1
268+
; RV64FD-NEXT: bnez a0, .LBB3_2
269+
; RV64FD-NEXT: # %bb.1: # %entry
270+
; RV64FD-NEXT: fmv.x.w a0, fa1
271+
; RV64FD-NEXT: j .LBB3_3
272+
; RV64FD-NEXT: .LBB3_2:
273+
; RV64FD-NEXT: fmv.x.w a0, fa0
274+
; RV64FD-NEXT: .LBB3_3: # %entry
275+
; RV64FD-NEXT: lui a1, 1048560
276+
; RV64FD-NEXT: or a0, a0, a1
277+
; RV64FD-NEXT: fmv.w.x fa0, a0
278+
; RV64FD-NEXT: ret
279+
;
139280
; RV32ZFINX_ZICOND-LABEL: select_half_i1:
140-
; RV32ZFINX_ZICOND: czero
141-
; RV32ZFINX_ZICOND: czero
142-
; RV32ZFINX_ZICOND: or
143-
; RV32ZFINX_ZICOND-NOT: b{{(eq|ne)z?}}
144-
; RV32ZFINX_ZICOND: ret
145-
146-
; RV32ZFINX_NOZICOND-LABEL: select_half_i1:
147-
; RV32ZFINX_NOZICOND: b{{(eq|ne)z?}}
148-
; RV32ZFINX_NOZICOND-NOT: czero.eqz
149-
; RV32ZFINX_NOZICOND-NOT: czero.nez
150-
151-
; RV32F-LABEL: select_half_i1:
152-
; RV32F: b{{(eq|ne)z?}}
153-
; RV32F-NOT: czero.eqz
154-
; RV32F-NOT: czero.nez
155-
281+
; RV32ZFINX_ZICOND: # %bb.0: # %entry
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; RV32ZFINX_ZICOND-NEXT: # kill: def $x12_w killed $x12_w def $x12
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; RV32ZFINX_ZICOND-NEXT: # kill: def $x11_w killed $x11_w def $x11
284+
; RV32ZFINX_ZICOND-NEXT: andi a0, a0, 1
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; RV32ZFINX_ZICOND-NEXT: czero.nez a2, a2, a0
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; RV32ZFINX_ZICOND-NEXT: czero.eqz a0, a1, a0
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; RV32ZFINX_ZICOND-NEXT: or a0, a0, a2
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; RV32ZFINX_ZICOND-NEXT: lui a1, 1048560
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; RV32ZFINX_ZICOND-NEXT: or a0, a0, a1
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; RV32ZFINX_ZICOND-NEXT: # kill: def $x10_w killed $x10_w killed $x10
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; RV32ZFINX_ZICOND-NEXT: ret
156292
entry:
157293
%sel = select i1 %cond, half %a, half %b
158294
ret half %sel
159-
}
295+
}

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