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[M68k] add test and change default copy size for ccr
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4 files changed

+152
-21
lines changed

4 files changed

+152
-21
lines changed

‎llvm/lib/Target/M68k/M68kInstrData.td‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -419,6 +419,8 @@ class MxMoveFromCCR_M<MxOperand MEMOp, MxEncMemOp DST_ENC>
419419

420420
class MxMoveFromCCRPseudo<MxOperand MEMOp>
421421
: MxPseudo<(outs), (ins MEMOp:$dst, CCRC:$src)>;
422+
class MxMoveFromCCR_RPseudo<MxOperand MEMOp>
423+
: MxPseudo<(outs MEMOp:$dst), (ins CCRC:$src)>;
422424
} // let Uses = [CCR]
423425

424426
let mayStore = 1 in
@@ -432,7 +434,7 @@ foreach AM = MxMoveSupportedAMs in {
432434

433435
// Only data register is allowed.
434436
def MOV16dc : MxMoveFromCCR_R;
435-
def MOV8dc : MxMoveFromCCRPseudo<MxOp8AddrMode_d.Op>;
437+
def MOV8dc : MxMoveFromCCR_RPseudo<MxOp8AddrMode_d.Op>;
436438

437439
//===----------------------------------------------------------------------===//
438440
// LEA

‎llvm/lib/Target/M68k/M68kInstrInfo.cpp‎

Lines changed: 22 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,9 @@
2323
#include "llvm/CodeGen/LivePhysRegs.h"
2424
#include "llvm/CodeGen/LiveVariables.h"
2525
#include "llvm/CodeGen/MachineInstrBuilder.h"
26+
#include "llvm/CodeGen/MachineOperand.h"
2627
#include "llvm/CodeGen/MachineRegisterInfo.h"
28+
#include "llvm/CodeGenTypes/MachineValueType.h"
2729
#include "llvm/MC/TargetRegistry.h"
2830
#include "llvm/Support/ErrorHandling.h"
2931
#include "llvm/Support/Regex.h"
@@ -571,6 +573,12 @@ bool M68kInstrInfo::ExpandPUSH_POP(MachineInstrBuilder &MIB,
571573
}
572574

573575
bool M68kInstrInfo::ExpandCCR(MachineInstrBuilder &MIB, bool IsToCCR) const {
576+
if (MIB->getOpcode() == M68k::MOV8cd) {
577+
// Promote used register to the next class
578+
MachineOperand &Opd = MIB->getOperand(1);
579+
Opd.setReg(getRegisterInfo().getMatchingSuperReg(
580+
Opd.getReg(), M68k::MxSubRegIndex8Lo, &M68k::DR16RegClass));
581+
}
574582

575583
// Replace the pseudo instruction with the real one
576584
if (IsToCCR)
@@ -579,11 +587,6 @@ bool M68kInstrInfo::ExpandCCR(MachineInstrBuilder &MIB, bool IsToCCR) const {
579587
// FIXME M68010 or later is required
580588
MIB->setDesc(get(M68k::MOV16dc));
581589

582-
// Promote used register to the next class
583-
auto &Opd = MIB->getOperand(1);
584-
Opd.setReg(getRegisterInfo().getMatchingSuperReg(
585-
Opd.getReg(), M68k::MxSubRegIndex8Lo, &M68k::DR16RegClass));
586-
587590
return true;
588591
}
589592

@@ -729,8 +732,8 @@ void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
729732
return;
730733
}
731734

732-
// Now deal with asymmetrically sized copies. The cases that follow are upcast
733-
// moves.
735+
// Now deal with asymmetrically sized copies. The cases that follow are
736+
// upcast moves.
734737
//
735738
// NOTE
736739
// These moves are not aware of type nature of these values and thus
@@ -757,24 +760,24 @@ void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
757760
bool ToSR = DstReg == M68k::SR;
758761

759762
if (FromCCR) {
760-
if (M68k::DR8RegClass.contains(DstReg))
763+
if (M68k::DR8RegClass.contains(DstReg)) {
761764
Opc = M68k::MOV8dc;
762-
else if (M68k::DR16RegClass.contains(DstReg))
765+
} else if (M68k::DR16RegClass.contains(DstReg)) {
763766
Opc = M68k::MOV16dc;
764-
else if (M68k::DR32RegClass.contains(DstReg))
767+
} else if (M68k::DR32RegClass.contains(DstReg)) {
765768
Opc = M68k::MOV16dc;
766-
else {
769+
} else {
767770
LLVM_DEBUG(dbgs() << "Cannot copy CCR to " << RI.getName(DstReg) << '\n');
768771
llvm_unreachable("Invalid register for MOVE from CCR");
769772
}
770773
} else if (ToCCR) {
771-
if (M68k::DR8RegClass.contains(SrcReg))
774+
if (M68k::DR8RegClass.contains(SrcReg)) {
772775
Opc = M68k::MOV8cd;
773-
else if (M68k::DR16RegClass.contains(SrcReg))
776+
} else if (M68k::DR16RegClass.contains(SrcReg)) {
774777
Opc = M68k::MOV16cd;
775-
else if (M68k::DR32RegClass.contains(SrcReg))
778+
} else if (M68k::DR32RegClass.contains(SrcReg)) {
776779
Opc = M68k::MOV16cd;
777-
else {
780+
} else {
778781
LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to CCR\n");
779782
llvm_unreachable("Invalid register for MOVE to CCR");
780783
}
@@ -886,10 +889,10 @@ unsigned M68kInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
886889
//
887890
// NOTE
888891
// Normally M68k uses A5 register as global base pointer but this will
889-
// create unnecessary spill if we use less then 4 registers in code; since A5
890-
// is callee-save anyway we could try to allocate caller-save first and if
891-
// lucky get one, otherwise it does not really matter which callee-save to
892-
// use.
892+
// create unnecessary spill if we use less then 4 registers in code; since
893+
// A5 is callee-save anyway we could try to allocate caller-save first and
894+
// if lucky get one, otherwise it does not really matter which callee-save
895+
// to use.
893896
MachineRegisterInfo &RegInfo = MF->getRegInfo();
894897
GlobalBaseReg = RegInfo.createVirtualRegister(&M68k::AR32_NOSPRegClass);
895898
MxFI->setGlobalBaseReg(GlobalBaseReg);

‎llvm/lib/Target/M68k/M68kRegisterInfo.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -101,7 +101,7 @@ class M68kRegisterInfo : public M68kGenRegisterInfo {
101101
const TargetRegisterClass *
102102
getCrossCopyRegClass(const TargetRegisterClass *RC) const override {
103103
if (RC == &M68k::CCRCRegClass)
104-
return &M68k::DR32RegClass;
104+
return &M68k::DR16RegClass;
105105
return RC;
106106
}
107107

‎llvm/test/CodeGen/M68k/Control/non-cmov-switch.ll‎

Lines changed: 126 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,126 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc < %s -mtriple=m68k-linux -mcpu=M68020 --verify-machineinstrs | FileCheck %s
3+
4+
define internal void @select_i32(i32 %self, ptr nonnull %value) {
5+
; CHECK-LABEL: select_i32:
6+
; CHECK: .cfi_startproc
7+
; CHECK-NEXT: ; %bb.0: ; %start
8+
; CHECK-NEXT: suba.l #4, %sp
9+
; CHECK-NEXT: .cfi_def_cfa_offset -8
10+
; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
11+
; CHECK-NEXT: cmpi.l #0, (8,%sp)
12+
; CHECK-NEXT: move.w %ccr, %d2
13+
; CHECK-NEXT: sne %d1
14+
; CHECK-NEXT: move.l (12,%sp), %d0
15+
; CHECK-NEXT: move.w %d2, %ccr
16+
; CHECK-NEXT: bne .LBB0_2
17+
; CHECK-NEXT: ; %bb.1: ; %start
18+
; CHECK-NEXT: and.l #255, %d1
19+
; CHECK-NEXT: cmpi.l #0, %d1
20+
; CHECK-NEXT: bne .LBB0_3
21+
; CHECK-NEXT: .LBB0_2: ; %null
22+
; CHECK-NEXT: suba.l %a0, %a0
23+
; CHECK-NEXT: move.l %d0, (%a0)
24+
; CHECK-NEXT: .LBB0_3: ; %exit
25+
; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
26+
; CHECK-NEXT: adda.l #4, %sp
27+
; CHECK-NEXT: rts
28+
start:
29+
%2 = icmp eq i32 %self, 0
30+
%3 = select i1 %2, i32 0, i32 1
31+
switch i32 %3, label %exit [
32+
i32 0, label %nonnull
33+
i32 1, label %null
34+
]
35+
36+
nonnull: ; preds = %start
37+
store ptr %value, ptr null, align 2
38+
br label %exit
39+
40+
null: ; preds = %start
41+
store ptr %value, ptr null, align 2
42+
br label %exit
43+
44+
exit: ; preds = %nonnull, %null
45+
ret void
46+
}
47+
48+
define internal void @select_i16(i16 %self, ptr nonnull %value) {
49+
; CHECK-LABEL: select_i16:
50+
; CHECK: .cfi_startproc
51+
; CHECK-NEXT: ; %bb.0: ; %start
52+
; CHECK-NEXT: suba.l #4, %sp
53+
; CHECK-NEXT: .cfi_def_cfa_offset -8
54+
; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
55+
; CHECK-NEXT: cmpi.w #0, (10,%sp)
56+
; CHECK-NEXT: move.w %ccr, %d2
57+
; CHECK-NEXT: sne %d1
58+
; CHECK-NEXT: move.l (12,%sp), %d0
59+
; CHECK-NEXT: move.w %d2, %ccr
60+
; CHECK-NEXT: bne .LBB1_2
61+
; CHECK-NEXT: ; %bb.1: ; %start
62+
; CHECK-NEXT: and.l #255, %d1
63+
; CHECK-NEXT: cmpi.w #0, %d1
64+
; CHECK-NEXT: bne .LBB1_3
65+
; CHECK-NEXT: .LBB1_2: ; %null
66+
; CHECK-NEXT: suba.l %a0, %a0
67+
; CHECK-NEXT: move.l %d0, (%a0)
68+
; CHECK-NEXT: .LBB1_3: ; %exit
69+
; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
70+
; CHECK-NEXT: adda.l #4, %sp
71+
; CHECK-NEXT: rts
72+
start:
73+
%2 = icmp eq i16 %self, 0
74+
%3 = select i1 %2, i16 0, i16 1
75+
switch i16 %3, label %exit [
76+
i16 0, label %nonnull
77+
i16 1, label %null
78+
]
79+
80+
nonnull: ; preds = %start
81+
store ptr %value, ptr null, align 2
82+
br label %exit
83+
84+
null: ; preds = %start
85+
store ptr %value, ptr null, align 2
86+
br label %exit
87+
88+
exit: ; preds = %nonnull, %null
89+
ret void
90+
}
91+
92+
define internal void @select_i8(i8 %self, ptr nonnull %value) {
93+
; CHECK-LABEL: select_i8:
94+
; CHECK: .cfi_startproc
95+
; CHECK-NEXT: ; %bb.0: ; %start
96+
; CHECK-NEXT: move.l (8,%sp), %d0
97+
; CHECK-NEXT: cmpi.b #0, (7,%sp)
98+
; CHECK-NEXT: sne %d1
99+
; CHECK-NEXT: bne .LBB2_2
100+
; CHECK-NEXT: ; %bb.1: ; %start
101+
; CHECK-NEXT: cmpi.b #0, %d1
102+
; CHECK-NEXT: bne .LBB2_3
103+
; CHECK-NEXT: .LBB2_2: ; %null
104+
; CHECK-NEXT: suba.l %a0, %a0
105+
; CHECK-NEXT: move.l %d0, (%a0)
106+
; CHECK-NEXT: .LBB2_3: ; %exit
107+
; CHECK-NEXT: rts
108+
start:
109+
%2 = icmp eq i8 %self, 0
110+
%3 = select i1 %2, i8 0, i8 1
111+
switch i8 %3, label %exit [
112+
i8 0, label %nonnull
113+
i8 1, label %null
114+
]
115+
116+
nonnull: ; preds = %start
117+
store ptr %value, ptr null, align 2
118+
br label %exit
119+
120+
null: ; preds = %start
121+
store ptr %value, ptr null, align 2
122+
br label %exit
123+
124+
exit: ; preds = %nonnull, %null
125+
ret void
126+
}

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