update feature name

Author: broxigarchen

llvm/lib/Target/AMDGPU/AMDGPU.td

@@ -586,8 +586,8 @@ def FeatureRealTrue16Insts : SubtargetFeature<"real-true16",
   "Use true 16-bit registers"
 >;
 
-def Feature16bitD16HWBug : SubtargetFeature<"d16-hw-bug",
-  "Enable16bitD16HWBug",
+def FeatureD16Writes32BitVgpr : SubtargetFeature<"d16-write-vgpr32",
+  "EnableD16Writes32BitVgpr",
   "true",
   "D16 instructions potentially have 32-bit data dependencies"
 >;
@@ -1941,7 +1941,7 @@ def FeatureISAVersion11_Common : FeatureSet<
    FeatureVcmpxPermlaneHazard,
    FeatureMemoryAtomicFAddF32DenormalSupport,
    FeatureRealTrue16Insts,
-   Feature16bitD16HWBug,
+   FeatureD16Writes32BitVgpr,
 ]>;
 
 // There are few workarounds that need to be
@@ -2578,10 +2578,10 @@ def UseFakeTrue16Insts : True16PredicateClass<"Subtarget->hasTrue16BitInsts() &&
   // FIXME When we default to RealTrue16 instead of Fake, change the line as follows.
   // AssemblerPredicate<(all_of FeatureTrue16BitInsts, (not FeatureRealTrue16Insts))>;
 
-def Has16bitD16HWBug: Predicate<"Subtarget->has16bitD16HWBug()">,
-  AssemblerPredicate<(all_of FeatureTrue16BitInsts, FeatureRealTrue16Insts, Feature16bitD16HWBug)>;
-def NotHas16bitD16HWBug: Predicate<"!Subtarget->has16bitD16HWBug()">,
-  AssemblerPredicate<(all_of FeatureTrue16BitInsts, FeatureRealTrue16Insts, (not Feature16bitD16HWBug))>;
+def HasD16Writes32BitVgpr: Predicate<"Subtarget->hasD16Writes32BitVgpr()">,
+  AssemblerPredicate<(all_of FeatureTrue16BitInsts, FeatureRealTrue16Insts, FeatureD16Writes32BitVgpr)>;
+def NotHasD16Writes32BitVgpr: Predicate<"!Subtarget->hasD16Writes32BitVgpr()">,
+  AssemblerPredicate<(all_of FeatureTrue16BitInsts, FeatureRealTrue16Insts, (not FeatureD16Writes32BitVgpr))>;
 
 def HasBF16TransInsts : Predicate<"Subtarget->hasBF16TransInsts()">,
   AssemblerPredicate<(all_of FeatureBF16TransInsts)>;

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

@@ -38,7 +38,9 @@ bool AMDGPUSubtarget::useRealTrue16Insts() const {
   return hasTrue16BitInsts() && EnableRealTrue16Insts;
 }
 
-bool AMDGPUSubtarget::has16bitD16HWBug() const { return Enable16bitD16HWBug; }
+bool AMDGPUSubtarget::hasD16Writes32BitVgpr() const {
+  return EnableD16Writes32BitVgpr;
+}
 
 // Returns the maximum per-workgroup LDS allocation size (in bytes) that still
 // allows the given function to achieve an occupancy of NWaves waves per

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h

@@ -59,7 +59,7 @@ class AMDGPUSubtarget {
   bool HasCvtPkF16F32Inst = false;
   bool HasF32ToF16BF16ConversionSRInsts = false;
   bool EnableRealTrue16Insts = false;
-  bool Enable16bitD16HWBug = false;
+  bool EnableD16Writes32BitVgpr = false;
   bool HasBF16TransInsts = false;
   bool HasBF16ConversionInsts = false;
   bool HasBF16PackedInsts = false;
@@ -225,7 +225,7 @@ class AMDGPUSubtarget {
   // supported and the support for fake True16 instructions is removed.
   bool useRealTrue16Insts() const;
 
-  bool has16bitD16HWBug() const;
+  bool hasD16Writes32BitVgpr() const;
 
   bool hasBF16TransInsts() const { return HasBF16TransInsts; }
 

llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp

@@ -846,7 +846,7 @@ RegInterval WaitcntBrackets::getRegInterval(const MachineInstr *MI,
     assert(Size % 16 == 0);
     Result.second = Result.first + (Size / 16);
 
-    if (Size == 16 && Context->ST->has16bitD16HWBug()) {
+    if (Size == 16 && Context->ST->hasD16Writes32BitVgpr()) {
       // Regardless of which lo16/hi16 is used, consider the full 32-bit
       // register used.
       if (AMDGPU::isHi16Reg(MCReg, *TRI))