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remove predicate In64BitMode since it's the same as IsPPC64
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4 files changed

+25
-26
lines changed

4 files changed

+25
-26
lines changed

‎llvm/lib/Target/PowerPC/PPC.td‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -365,7 +365,6 @@ def IsLittleEndian : Predicate<"Subtarget->isLittleEndian()">;
365365
def IsBigEndian : Predicate<"!Subtarget->isLittleEndian()">;
366366
def IsPPC32 : Predicate<"!Subtarget->isPPC64()">;
367367
def IsPPC64 : Predicate<"Subtarget->isPPC64()">;
368-
def In64BitMode : Predicate<"Subtarget->isPPC64()">;
369368
def IsBookE : Predicate<"Subtarget->isBookE()">;
370369
def IsNotBookE : Predicate<"!Subtarget->isBookE()">;
371370
def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">;
@@ -426,7 +425,7 @@ def NotAIX : Predicate<"!Subtarget->isAIXABI()">;
426425
//===----------------------------------------------------------------------===//
427426

428427
defvar PPC32 = DefaultMode;
429-
def PPC64 : HwMode<[In64BitMode]>;
428+
def PPC64 : HwMode<[IsPPC64]>;
430429

431430
// Since new processors generally contain a superset of features of those that
432431
// came before them, the idea is to make implementations of new processors

‎llvm/lib/Target/PowerPC/PPCInstr64Bit.td‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -76,23 +76,23 @@ let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
7676
let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in {
7777
let isReturn = 1, isPredicable = 1, Uses = [LR8, RM] in
7878
def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
79-
[(PPCretglue)]>, Requires<[In64BitMode]>;
79+
[(PPCretglue)]>, Requires<[IsPPC64]>;
8080
let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
8181
let isPredicable = 1 in
8282
def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
8383
[]>,
84-
Requires<[In64BitMode]>;
84+
Requires<[IsPPC64]>;
8585
def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins (pred $BIBO, $CR):$cond),
8686
"b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
8787
[]>,
88-
Requires<[In64BitMode]>;
88+
Requires<[IsPPC64]>;
8989

9090
def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$BI),
9191
"bcctr 12, $BI, 0", IIC_BrB, []>,
92-
Requires<[In64BitMode]>;
92+
Requires<[IsPPC64]>;
9393
def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$BI),
9494
"bcctr 4, $BI, 0", IIC_BrB, []>,
95-
Requires<[In64BitMode]>;
95+
Requires<[IsPPC64]>;
9696
}
9797
}
9898

@@ -160,20 +160,20 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR8], hasSideEffects = 0 in {
160160
let isPredicable = 1 in
161161
def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
162162
"bctrl", IIC_BrB, [(PPCbctrl)]>,
163-
Requires<[In64BitMode]>;
163+
Requires<[IsPPC64]>;
164164

165165
let isCodeGenOnly = 1 in {
166166
def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins (pred $BIBO, $CR):$cond),
167167
"b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
168168
[]>,
169-
Requires<[In64BitMode]>;
169+
Requires<[IsPPC64]>;
170170

171171
def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$BI),
172172
"bcctrl 12, $BI, 0", IIC_BrB, []>,
173-
Requires<[In64BitMode]>;
173+
Requires<[IsPPC64]>;
174174
def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$BI),
175175
"bcctrl 4, $BI, 0", IIC_BrB, []>,
176-
Requires<[In64BitMode]>;
176+
Requires<[IsPPC64]>;
177177
}
178178
}
179179
}
@@ -207,7 +207,7 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR8, RM], hasSideEffects = 0,
207207
let isPredicable = 1 in
208208
def BCTRL8_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
209209
"bctrl", IIC_BrB, [(PPCbctrl_rm)]>,
210-
Requires<[In64BitMode]>;
210+
Requires<[IsPPC64]>;
211211
}
212212
}
213213

@@ -218,7 +218,7 @@ let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
218218
(ins (memrix $D, $RA):$src),
219219
"bctrl\n\tld 2, $src", IIC_BrB,
220220
[(PPCbctrl_load_toc iaddrX4:$src)]>,
221-
Requires<[In64BitMode]>;
221+
Requires<[IsPPC64]>;
222222
}
223223

224224
let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
@@ -228,7 +228,7 @@ let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
228228
(ins (memrix $D, $RA):$src),
229229
"bctrl\n\tld 2, $src", IIC_BrB,
230230
[(PPCbctrl_load_toc_rm iaddrX4:$src)]>,
231-
Requires<[In64BitMode]>;
231+
Requires<[IsPPC64]>;
232232
}
233233

234234
} // Interpretation64Bit
@@ -449,7 +449,7 @@ let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
449449
isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
450450
def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
451451
[]>,
452-
Requires<[In64BitMode]>;
452+
Requires<[IsPPC64]>;
453453

454454
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
455455
isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
@@ -516,15 +516,15 @@ let hasSideEffects = 1 in {
516516
def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf),
517517
"#EH_SJLJ_SETJMP64",
518518
[(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
519-
Requires<[In64BitMode]>;
519+
Requires<[IsPPC64]>;
520520
}
521521

522522
let hasSideEffects = 1, isBarrier = 1 in {
523523
let isTerminator = 1 in
524524
def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf),
525525
"#EH_SJLJ_LONGJMP64",
526526
[(PPCeh_sjlj_longjmp addr:$buf)]>,
527-
Requires<[In64BitMode]>;
527+
Requires<[IsPPC64]>;
528528
}
529529

530530
def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RST), (ins i32imm:$SPR),
@@ -1948,7 +1948,7 @@ def : Pat<(atomic_load_nonext_64 XForm:$src), (LDX memrr:$src)>;
19481948
def : Pat<(atomic_store_64 i64:$val, DSForm:$ptr), (STD g8rc:$val, memrix:$ptr)>;
19491949
def : Pat<(atomic_store_64 i64:$val, XForm:$ptr), (STDX g8rc:$val, memrr:$ptr)>;
19501950

1951-
let Predicates = [IsISA3_0, In64BitMode] in {
1951+
let Predicates = [IsISA3_0, IsPPC64] in {
19521952
def : Pat<(i64 (int_ppc_cmpeqb g8rc:$a, g8rc:$b)),
19531953
(i64 (SETB8 (CMPEQB $a, $b)))>;
19541954
def : Pat<(i64 (int_ppc_setb g8rc:$a, g8rc:$b)),
@@ -1961,7 +1961,7 @@ def : Pat<(i64 (int_ppc_maddld g8rc:$a, g8rc:$b, g8rc:$c)),
19611961
(i64 (MADDLD8 $a, $b, $c))>;
19621962
}
19631963

1964-
let Predicates = [In64BitMode] in {
1964+
let Predicates = [IsPPC64] in {
19651965
def : Pat<(i64 (int_ppc_mulhd g8rc:$a, g8rc:$b)),
19661966
(i64 (MULHD $a, $b))>;
19671967
def : Pat<(i64 (int_ppc_mulhdu g8rc:$a, g8rc:$b)),

‎llvm/lib/Target/PowerPC/PPCInstrInfo.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5142,7 +5142,7 @@ def RotateInsertByte1 {
51425142
}
51435143

51445144
// Clear the upper half of the register when in 64-bit mode
5145-
let Predicates = [In64BitMode] in
5145+
let Predicates = [IsPPC64] in
51465146
def : Pat<(i32 (bitreverse i32:$A)), (RLDICL_32 RotateInsertByte1.Left, 0, 32)>;
51475147
let Predicates = [IsPPC32] in
51485148
def : Pat<(i32 (bitreverse i32:$A)), RotateInsertByte1.Left>;

‎llvm/lib/Target/PowerPC/PPCInstrVSX.td‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1279,13 +1279,13 @@ let Predicates = [HasVSX, HasP8Vector] in {
12791279
def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$RA), (ins vsfrc:$XT),
12801280
"mfvsrd $RA, $XT", IIC_VecGeneral,
12811281
[(set i64:$RA, (PPCmfvsr f64:$XT))]>,
1282-
Requires<[In64BitMode]>;
1282+
Requires<[IsPPC64]>;
12831283
// FIXME: Setting the hasSideEffects flag here to match current behaviour.
12841284
let isCodeGenOnly = 1, hasSideEffects = 1 in
12851285
def MFVRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$RA), (ins vsrc:$XT),
12861286
"mfvsrd $RA, $XT", IIC_VecGeneral,
12871287
[]>,
1288-
Requires<[In64BitMode]>;
1288+
Requires<[IsPPC64]>;
12891289
def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$RA), (ins vsfrc:$XT),
12901290
"mfvsrwz $RA, $XT", IIC_VecGeneral,
12911291
[(set i32:$RA, (PPCmfvsr f64:$XT))]>, ZExt32To64;
@@ -1297,13 +1297,13 @@ let Predicates = [HasVSX, HasP8Vector] in {
12971297
def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$RA),
12981298
"mtvsrd $XT, $RA", IIC_VecGeneral,
12991299
[(set f64:$XT, (PPCmtvsra i64:$RA))]>,
1300-
Requires<[In64BitMode]>;
1300+
Requires<[IsPPC64]>;
13011301
// FIXME: Setting the hasSideEffects flag here to match current behaviour.
13021302
let isCodeGenOnly = 1, hasSideEffects = 1 in
13031303
def MTVRD : XX1_RS6_RD5_XO<31, 179, (outs vsrc:$XT), (ins g8rc:$RA),
13041304
"mtvsrd $XT, $RA", IIC_VecGeneral,
13051305
[]>,
1306-
Requires<[In64BitMode]>;
1306+
Requires<[IsPPC64]>;
13071307
def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$RA),
13081308
"mtvsrwa $XT, $RA", IIC_VecGeneral,
13091309
[(set f64:$XT, (PPCmtvsra i32:$RA))]>;
@@ -1330,11 +1330,11 @@ def MTVSRWS: XX1_RS6_RD5_XO<31, 403, (outs vsrc:$XT), (ins gprc:$RA),
13301330

13311331
def MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins g8rc_nox0:$RA, g8rc:$RB),
13321332
"mtvsrdd $XT, $RA, $RB", IIC_VecGeneral,
1333-
[]>, Requires<[In64BitMode]>;
1333+
[]>, Requires<[IsPPC64]>;
13341334

13351335
def MFVSRLD: XX1_RS6_RD5_XO<31, 307, (outs g8rc:$RA), (ins vsrc:$XT),
13361336
"mfvsrld $RA, $XT", IIC_VecGeneral,
1337-
[]>, Requires<[In64BitMode]>;
1337+
[]>, Requires<[IsPPC64]>;
13381338

13391339
} // HasVSX, IsISA3_0, HasDirectMove
13401340

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