fix formatting

ro-i · ro-i · commit 61161b8fb56e · 2025-02-12T07:35:16.000-06:00
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -2937,7 +2937,8 @@ SDValue SITargetLowering::LowerFormalArguments(
 
   for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
     const ISD::InputArg &Arg = Ins[i];
-    if ((Arg.isOrigArg() && Skipped[Arg.getOrigArgIndex()]) || IsUnsupportedHsa) {
+    if ((Arg.isOrigArg() && Skipped[Arg.getOrigArgIndex()]) ||
+        IsUnsupportedHsa) {
       InVals.push_back(DAG.getUNDEF(Arg.VT));
       continue;
     }

Original file line number	Diff line number	Diff line change
`@@ -2937,7 +2937,8 @@ SDValue SITargetLowering::LowerFormalArguments(`
`2937`	`2937`
`2938`	`2938`	`for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {`
`2939`	`2939`	`const ISD::InputArg &Arg = Ins[i];`
`2940`		`- if ((Arg.isOrigArg() && Skipped[Arg.getOrigArgIndex()]) \|\| IsUnsupportedHsa) {`
	`2940`	`+ if ((Arg.isOrigArg() && Skipped[Arg.getOrigArgIndex()]) \|\|`
	`2941`	`+ IsUnsupportedHsa) {`
`2941`	`2942`	`InVals.push_back(DAG.getUNDEF(Arg.VT));`
`2942`	`2943`	`continue;`
`2943`	`2944`	`}`