[X86]: Updated tests

Author: kper

llvm/test/CodeGen/X86/abds-vector-128.ll

@@ -756,9 +756,9 @@ define <2 x i64> @abd_cmp_v2i64_multiuse_cmp(<2 x i64> %a, <2 x i64> %b) nounwin
 ; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm3[0,0,2,2]
 ; SSE2-NEXT:    pand %xmm6, %xmm0
 ; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm3[1,1,3,3]
-; SSE2-NEXT:    por %xmm0, %xmm1
-; SSE2-NEXT:    pcmpeqd %xmm0, %xmm0
-; SSE2-NEXT:    pxor %xmm1, %xmm0
+; SSE2-NEXT:    pcmpeqd %xmm2, %xmm2
+; SSE2-NEXT:    pxor %xmm1, %xmm2
+; SSE2-NEXT:    pandn %xmm2, %xmm0
 ; SSE2-NEXT:    paddq %xmm4, %xmm0
 ; SSE2-NEXT:    retq
 ;

llvm/test/CodeGen/X86/avx512-mask-bit-manip.ll

@@ -714,18 +714,19 @@ define <64 x i8> @tzmsk_v64i8(<64 x i8> %a0, <64 x i8> %a1) {
 ; AVX512F-NEXT:    vpmovmskb %ymm4, %ecx
 ; AVX512F-NEXT:    shlq $32, %rcx
 ; AVX512F-NEXT:    leaq (%rax,%rcx), %rdx
-; AVX512F-NEXT:    addq %rcx, %rax
-; AVX512F-NEXT:    addq $-1, %rax
-; AVX512F-NEXT:    andnq %rax, %rdx, %rax
-; AVX512F-NEXT:    movq %rax, %rcx
-; AVX512F-NEXT:    movl %eax, %edx
-; AVX512F-NEXT:    kmovw %eax, %k1
-; AVX512F-NEXT:    shrq $32, %rax
-; AVX512F-NEXT:    shrq $48, %rcx
-; AVX512F-NEXT:    shrl $16, %edx
-; AVX512F-NEXT:    kmovw %edx, %k2
-; AVX512F-NEXT:    kmovw %ecx, %k3
-; AVX512F-NEXT:    kmovw %eax, %k4
+; AVX512F-NEXT:    addq $-1, %rdx
+; AVX512F-NEXT:    notq %rcx
+; AVX512F-NEXT:    andnq %rcx, %rax, %rax
+; AVX512F-NEXT:    andq %rax, %rdx
+; AVX512F-NEXT:    movq %rdx, %rax
+; AVX512F-NEXT:    movl %edx, %ecx
+; AVX512F-NEXT:    kmovw %edx, %k1
+; AVX512F-NEXT:    shrq $32, %rdx
+; AVX512F-NEXT:    shrq $48, %rax
+; AVX512F-NEXT:    shrl $16, %ecx
+; AVX512F-NEXT:    kmovw %ecx, %k2
+; AVX512F-NEXT:    kmovw %eax, %k3
+; AVX512F-NEXT:    kmovw %edx, %k4
 ; AVX512F-NEXT:    vpaddb %ymm2, %ymm3, %ymm2
 ; AVX512F-NEXT:    vpaddb %ymm1, %ymm0, %ymm1
 ; AVX512F-NEXT:    vinserti64x4 $1, %ymm2, %zmm1, %zmm1

llvm/test/CodeGen/X86/bmi-reassoc-demorgan.ll

@@ -88,8 +88,11 @@ define <4 x i32> @bool_logic_and_math_vec(<4 x i32> %a, <4 x i32> %b, <4 x i32>
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vpcmpeqd %xmm1, %xmm0, %xmm0
 ; CHECK-NEXT:    vpcmpeqd %xmm3, %xmm2, %xmm1
-; CHECK-NEXT:    vpor %xmm1, %xmm0, %xmm0
-; CHECK-NEXT:    vpsrld $31, %xmm0, %xmm0
+; CHECK-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
+; CHECK-NEXT:    vpxor %xmm2, %xmm1, %xmm1
+; CHECK-NEXT:    vpandn %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1]
+; CHECK-NEXT:    vpandn %xmm1, %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %cmp1 = icmp ne <4 x i32> %a, %b
   %cmp2 = icmp ne <4 x i32> %c, %d

llvm/test/CodeGen/X86/bool-ext-inc.ll

@@ -183,14 +183,32 @@ define i32 @or_and_multiuse_and_multiuse_i32(i32 %x, i32 %y) nounwind {
 }
 
 define i64 @or_build_pair_not(i32 %a0, i32 %a1) {
-; CHECK-LABEL: or_build_pair_not:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    # kill: def $esi killed $esi def $rsi
-; CHECK-NEXT:    shlq $32, %rsi
-; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    orq %rsi, %rax
-; CHECK-NEXT:    notq %rax
-; CHECK-NEXT:    retq
+; SSE-LABEL: or_build_pair_not:
+; SSE:       # %bb.0:
+; SSE-NEXT:    # kill: def $esi killed $esi def $rsi
+; SSE-NEXT:    shlq $32, %rsi
+; SSE-NEXT:    movl %edi, %eax
+; SSE-NEXT:    orq %rsi, %rax
+; SSE-NEXT:    notq %rax
+; SSE-NEXT:    retq
+;
+; AVX1-LABEL: or_build_pair_not:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    # kill: def $esi killed $esi def $rsi
+; AVX1-NEXT:    shlq $32, %rsi
+; AVX1-NEXT:    movl %edi, %eax
+; AVX1-NEXT:    orq %rsi, %rax
+; AVX1-NEXT:    notq %rax
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: or_build_pair_not:
+; AVX2:       # %bb.0:
+; AVX2-NEXT:    # kill: def $esi killed $esi def $rsi
+; AVX2-NEXT:    shlq $32, %rsi
+; AVX2-NEXT:    notq %rsi
+; AVX2-NEXT:    movl %edi, %eax
+; AVX2-NEXT:    andnq %rsi, %rax, %rax
+; AVX2-NEXT:    retq
   %n0 = xor i32 %a0, -1
   %n1 = xor i32 %a1, -1
   %x0 = zext i32 %n0 to i64
@@ -262,10 +280,9 @@ define i64 @PR89533(<64 x i8> %a0) {
 ; AVX2-NEXT:    vpcmpeqb %ymm2, %ymm1, %ymm0
 ; AVX2-NEXT:    vpmovmskb %ymm0, %ecx
 ; AVX2-NEXT:    shlq $32, %rcx
-; AVX2-NEXT:    orq %rax, %rcx
 ; AVX2-NEXT:    notq %rcx
-; AVX2-NEXT:    xorl %eax, %eax
-; AVX2-NEXT:    tzcntq %rcx, %rax
+; AVX2-NEXT:    andnq %rcx, %rax, %rax
+; AVX2-NEXT:    tzcntq %rax, %rax
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
   %cmp = icmp ne <64 x i8> %a0, <i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95, i8 95>

llvm/test/CodeGen/X86/combine-or.ll

@@ -440,9 +440,9 @@ define <4 x i32> @combine_vec_lshr_lzcnt_bit1(<4 x i32> %x) {
 ; SSE2-NEXT:    por %xmm1, %xmm0
 ; SSE2-NEXT:    movdqa %xmm0, %xmm1
 ; SSE2-NEXT:    psrld $16, %xmm1
-; SSE2-NEXT:    por %xmm1, %xmm0
-; SSE2-NEXT:    pcmpeqd %xmm1, %xmm1
-; SSE2-NEXT:    pxor %xmm1, %xmm0
+; SSE2-NEXT:    pcmpeqd %xmm2, %xmm2
+; SSE2-NEXT:    pxor %xmm1, %xmm2
+; SSE2-NEXT:    pandn %xmm2, %xmm0
 ; SSE2-NEXT:    movdqa %xmm0, %xmm1
 ; SSE2-NEXT:    psrlw $1, %xmm1
 ; SSE2-NEXT:    pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1

llvm/test/CodeGen/X86/combine-srl.ll

@@ -1490,9 +1490,9 @@ define <4 x i32> @vp_ctlz_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
 ; SSE-NEXT:    por %xmm1, %xmm0
 ; SSE-NEXT:    movdqa %xmm0, %xmm1
 ; SSE-NEXT:    psrld $16, %xmm1
-; SSE-NEXT:    por %xmm1, %xmm0
-; SSE-NEXT:    pcmpeqd %xmm1, %xmm1
-; SSE-NEXT:    pxor %xmm1, %xmm0
+; SSE-NEXT:    pcmpeqd %xmm2, %xmm2
+; SSE-NEXT:    pxor %xmm1, %xmm2
+; SSE-NEXT:    pandn %xmm2, %xmm0
 ; SSE-NEXT:    movdqa %xmm0, %xmm1
 ; SSE-NEXT:    psrlw $1, %xmm1
 ; SSE-NEXT:    pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1