Optimize once more

AZero13 · AZero13 · commit 654ac9295990 · 2025-11-11T16:12:51.000-05:00
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -9901,27 +9901,26 @@ SDValue TargetLowering::expandBSWAP(SDNode *N, SelectionDAG &DAG) const {
   case MVT::i32:
     // This is meant for ARM specifically, which has ROTR but no ROTL.
     if (isOperationLegalOrCustom(ISD::ROTR, VT)) {
-      // ror rtmp, r0, #16
+      // eor r3, r0, r0, ror #16
       SDValue Ror16 =
           DAG.getNode(ISD::ROTR, dl, VT, Op, DAG.getConstant(16, dl, SHVT));
-      // eor r1, r0, rtmp   ; r1 = r0 ^ (r0 ror 16)
       SDValue Xor1 = DAG.getNode(ISD::XOR, dl, VT, Op, Ror16);
 
-      // bic r1, r1, #0xff0000 (clear bits 16-23)
-      // So we need the negated value: ~0x00FF0000 = 0xFF00FFFF
-      SDValue Mask = DAG.getConstant(0xFF00FFFFu, dl, VT);
-      SDValue BicResult = DAG.getNode(ISD::AND, dl, VT, Xor1, Mask);
+      // lsr r3, r3, #8
+      SDValue Lsr8 =
+          DAG.getNode(ISD::SRL, dl, VT, Xor1, DAG.getConstant(8, dl, SHVT));
 
-      // mov r1, r1, lsr #8
-      SDValue Lsr8 = DAG.getNode(ISD::SRL, dl, VT, BicResult,
-                                 DAG.getConstant(8, dl, SHVT));
+      // bic r3, r3, #65280  (0xFF00)
+      // So we need the negated value: ~0x0000FF00 = 0xFFFF00FF
+      SDValue Mask = DAG.getConstant(0xFFFF00FFu, dl, VT);
+      SDValue BicResult = DAG.getNode(ISD::AND, dl, VT, Lsr8, Mask);
 
       // ror r0, r0, #8
       SDValue Ror8 =
           DAG.getNode(ISD::ROTR, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
 
-      // eor r0, Lsr8, Ror8
-      return DAG.getNode(ISD::XOR, dl, VT, Lsr8, Ror8);
+      // eor r0, r3, r0, ror #8
+      return DAG.getNode(ISD::XOR, dl, VT, BicResult, Ror8);
     }
     Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
     Tmp3 = DAG.getNode(ISD::AND, dl, VT, Op,
diff --git a/llvm/test/CodeGen/ARM/load-combine-big-endian.ll b/llvm/test/CodeGen/ARM/load-combine-big-endian.ll
@@ -53,9 +53,9 @@ define i32 @load_i32_by_i8_bswap(ptr %arg) {
 ; CHECK-LABEL: load_i32_by_i8_bswap:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    ldr r0, [r0]
+; CHECK-NEXT:    mvn r2, #65280
 ; CHECK-NEXT:    eor r1, r0, r0, ror #16
-; CHECK-NEXT:    bic r1, r1, #16711680
-; CHECK-NEXT:    lsr r1, r1, #8
+; CHECK-NEXT:    and r1, r2, r1, lsr #8
 ; CHECK-NEXT:    eor r0, r1, r0, ror #8
 ; CHECK-NEXT:    mov pc, lr
 ;
@@ -220,14 +220,13 @@ define i64 @load_i64_by_i8_bswap(ptr %arg) {
 ; CHECK-LABEL: load_i64_by_i8_bswap:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    ldr r1, [r0]
+; CHECK-NEXT:    mvn r3, #65280
 ; CHECK-NEXT:    ldr r0, [r0, #4]
 ; CHECK-NEXT:    eor r2, r0, r0, ror #16
-; CHECK-NEXT:    bic r2, r2, #16711680
-; CHECK-NEXT:    lsr r2, r2, #8
+; CHECK-NEXT:    and r2, r3, r2, lsr #8
 ; CHECK-NEXT:    eor r0, r2, r0, ror #8
 ; CHECK-NEXT:    eor r2, r1, r1, ror #16
-; CHECK-NEXT:    bic r2, r2, #16711680
-; CHECK-NEXT:    lsr r2, r2, #8
+; CHECK-NEXT:    and r2, r3, r2, lsr #8
 ; CHECK-NEXT:    eor r1, r2, r1, ror #8
 ; CHECK-NEXT:    mov pc, lr
 ;
@@ -369,9 +368,9 @@ define i32 @load_i32_by_i8_nonzero_offset(ptr %arg) {
 ; CHECK-LABEL: load_i32_by_i8_nonzero_offset:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    ldr r0, [r0, #1]
+; CHECK-NEXT:    mvn r2, #65280
 ; CHECK-NEXT:    eor r1, r0, r0, ror #16
-; CHECK-NEXT:    bic r1, r1, #16711680
-; CHECK-NEXT:    lsr r1, r1, #8
+; CHECK-NEXT:    and r1, r2, r1, lsr #8
 ; CHECK-NEXT:    eor r0, r1, r0, ror #8
 ; CHECK-NEXT:    mov pc, lr
 ;
@@ -423,9 +422,9 @@ define i32 @load_i32_by_i8_neg_offset(ptr %arg) {
 ; CHECK-LABEL: load_i32_by_i8_neg_offset:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    ldr r0, [r0, #-4]
+; CHECK-NEXT:    mvn r2, #65280
 ; CHECK-NEXT:    eor r1, r0, r0, ror #16
-; CHECK-NEXT:    bic r1, r1, #16711680
-; CHECK-NEXT:    lsr r1, r1, #8
+; CHECK-NEXT:    and r1, r2, r1, lsr #8
 ; CHECK-NEXT:    eor r0, r1, r0, ror #8
 ; CHECK-NEXT:    mov pc, lr
 ;
@@ -573,9 +572,9 @@ define i32 @load_i32_by_bswap_i16(ptr %arg) {
 ; CHECK-LABEL: load_i32_by_bswap_i16:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    ldr r0, [r0]
+; CHECK-NEXT:    mvn r2, #65280
 ; CHECK-NEXT:    eor r1, r0, r0, ror #16
-; CHECK-NEXT:    bic r1, r1, #16711680
-; CHECK-NEXT:    lsr r1, r1, #8
+; CHECK-NEXT:    and r1, r2, r1, lsr #8
 ; CHECK-NEXT:    eor r0, r1, r0, ror #8
 ; CHECK-NEXT:    mov pc, lr
 ;
@@ -649,10 +648,10 @@ define i32 @load_i32_by_i8_base_offset_index(ptr %arg, i32 %i) {
 ; CHECK-LABEL: load_i32_by_i8_base_offset_index:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    add r0, r0, r1
+; CHECK-NEXT:    mvn r2, #65280
 ; CHECK-NEXT:    ldr r0, [r0, #12]
 ; CHECK-NEXT:    eor r1, r0, r0, ror #16
-; CHECK-NEXT:    bic r1, r1, #16711680
-; CHECK-NEXT:    lsr r1, r1, #8
+; CHECK-NEXT:    and r1, r2, r1, lsr #8
 ; CHECK-NEXT:    eor r0, r1, r0, ror #8
 ; CHECK-NEXT:    mov pc, lr
 ;
@@ -712,10 +711,10 @@ define i32 @load_i32_by_i8_base_offset_index_2(ptr %arg, i32 %i) {
 ; CHECK-LABEL: load_i32_by_i8_base_offset_index_2:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    add r0, r1, r0
+; CHECK-NEXT:    mvn r2, #65280
 ; CHECK-NEXT:    ldr r0, [r0, #13]
 ; CHECK-NEXT:    eor r1, r0, r0, ror #16
-; CHECK-NEXT:    bic r1, r1, #16711680
-; CHECK-NEXT:    lsr r1, r1, #8
+; CHECK-NEXT:    and r1, r2, r1, lsr #8
 ; CHECK-NEXT:    eor r0, r1, r0, ror #8
 ; CHECK-NEXT:    mov pc, lr
 ;
diff --git a/llvm/test/CodeGen/ARM/load-combine.ll b/llvm/test/CodeGen/ARM/load-combine.ll
@@ -137,9 +137,9 @@ define i32 @load_i32_by_i8_bswap(ptr %arg) {
 ; CHECK-LABEL: load_i32_by_i8_bswap:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    ldr r0, [r0]
+; CHECK-NEXT:    mvn r2, #65280
 ; CHECK-NEXT:    eor r1, r0, r0, ror #16
-; CHECK-NEXT:    bic r1, r1, #16711680
-; CHECK-NEXT:    lsr r1, r1, #8
+; CHECK-NEXT:    and r1, r2, r1, lsr #8
 ; CHECK-NEXT:    eor r0, r1, r0, ror #8
 ; CHECK-NEXT:    mov pc, lr
 ;
@@ -153,15 +153,15 @@ define i32 @load_i32_by_i8_bswap(ptr %arg) {
 ; CHECK-THUMBv5-NEXT:    movs r3, r0
 ; CHECK-THUMBv5-NEXT:    rors r3, r1
 ; CHECK-THUMBv5-NEXT:    eors r3, r0
+; CHECK-THUMBv5-NEXT:    lsrs r1, r3, #8
 ; CHECK-THUMBv5-NEXT:    ldr r0, .LCPI2_0
-; CHECK-THUMBv5-NEXT:    ands r0, r3
-; CHECK-THUMBv5-NEXT:    lsrs r0, r0, #8
+; CHECK-THUMBv5-NEXT:    ands r0, r1
 ; CHECK-THUMBv5-NEXT:    eors r0, r2
 ; CHECK-THUMBv5-NEXT:    bx lr
 ; CHECK-THUMBv5-NEXT:    .p2align 2
 ; CHECK-THUMBv5-NEXT:  @ %bb.1:
 ; CHECK-THUMBv5-NEXT:  .LCPI2_0:
-; CHECK-THUMBv5-NEXT:    .long 4278255360 @ 0xff00ff00
+; CHECK-THUMBv5-NEXT:    .long 16711935 @ 0xff00ff
 ;
 ; CHECK-ARMv6-LABEL: load_i32_by_i8_bswap:
 ; CHECK-ARMv6:       @ %bb.0:
@@ -281,47 +281,46 @@ define i64 @load_i64_by_i8_bswap(ptr %arg) {
 ; CHECK-LABEL: load_i64_by_i8_bswap:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    ldr r1, [r0]
+; CHECK-NEXT:    mvn r3, #65280
 ; CHECK-NEXT:    ldr r0, [r0, #4]
 ; CHECK-NEXT:    eor r2, r0, r0, ror #16
-; CHECK-NEXT:    bic r2, r2, #16711680
-; CHECK-NEXT:    lsr r2, r2, #8
+; CHECK-NEXT:    and r2, r3, r2, lsr #8
 ; CHECK-NEXT:    eor r0, r2, r0, ror #8
 ; CHECK-NEXT:    eor r2, r1, r1, ror #16
-; CHECK-NEXT:    bic r2, r2, #16711680
-; CHECK-NEXT:    lsr r2, r2, #8
+; CHECK-NEXT:    and r2, r3, r2, lsr #8
 ; CHECK-NEXT:    eor r1, r2, r1, ror #8
 ; CHECK-NEXT:    mov pc, lr
 ;
 ; CHECK-THUMBv5-LABEL: load_i64_by_i8_bswap:
 ; CHECK-THUMBv5:       @ %bb.0:
 ; CHECK-THUMBv5-NEXT:    push {r4, r5, r7, lr}
-; CHECK-THUMBv5-NEXT:    ldr r1, [r0, #4]
-; CHECK-THUMBv5-NEXT:    movs r3, #8
-; CHECK-THUMBv5-NEXT:    movs r4, r1
-; CHECK-THUMBv5-NEXT:    rors r4, r3
-; CHECK-THUMBv5-NEXT:    movs r5, #16
+; CHECK-THUMBv5-NEXT:    movs r1, r0
+; CHECK-THUMBv5-NEXT:    ldr r0, [r0, #4]
+; CHECK-THUMBv5-NEXT:    movs r2, #8
+; CHECK-THUMBv5-NEXT:    movs r3, r0
+; CHECK-THUMBv5-NEXT:    rors r3, r2
+; CHECK-THUMBv5-NEXT:    movs r4, #16
+; CHECK-THUMBv5-NEXT:    movs r5, r0
+; CHECK-THUMBv5-NEXT:    rors r5, r4
+; CHECK-THUMBv5-NEXT:    eors r5, r0
+; CHECK-THUMBv5-NEXT:    lsrs r0, r5, #8
+; CHECK-THUMBv5-NEXT:    ldr r5, .LCPI4_0
+; CHECK-THUMBv5-NEXT:    ands r0, r5
+; CHECK-THUMBv5-NEXT:    eors r0, r3
+; CHECK-THUMBv5-NEXT:    ldr r1, [r1]
+; CHECK-THUMBv5-NEXT:    movs r3, r1
+; CHECK-THUMBv5-NEXT:    rors r3, r2
 ; CHECK-THUMBv5-NEXT:    movs r2, r1
-; CHECK-THUMBv5-NEXT:    rors r2, r5
+; CHECK-THUMBv5-NEXT:    rors r2, r4
 ; CHECK-THUMBv5-NEXT:    eors r2, r1
-; CHECK-THUMBv5-NEXT:    ldr r1, .LCPI4_0
-; CHECK-THUMBv5-NEXT:    ands r2, r1
-; CHECK-THUMBv5-NEXT:    lsrs r2, r2, #8
-; CHECK-THUMBv5-NEXT:    eors r2, r4
-; CHECK-THUMBv5-NEXT:    ldr r0, [r0]
-; CHECK-THUMBv5-NEXT:    movs r4, r0
-; CHECK-THUMBv5-NEXT:    rors r4, r3
-; CHECK-THUMBv5-NEXT:    movs r3, r0
-; CHECK-THUMBv5-NEXT:    rors r3, r5
-; CHECK-THUMBv5-NEXT:    eors r3, r0
-; CHECK-THUMBv5-NEXT:    ands r3, r1
-; CHECK-THUMBv5-NEXT:    lsrs r1, r3, #8
-; CHECK-THUMBv5-NEXT:    eors r1, r4
-; CHECK-THUMBv5-NEXT:    movs r0, r2
+; CHECK-THUMBv5-NEXT:    lsrs r1, r2, #8
+; CHECK-THUMBv5-NEXT:    ands r1, r5
+; CHECK-THUMBv5-NEXT:    eors r1, r3
 ; CHECK-THUMBv5-NEXT:    pop {r4, r5, r7, pc}
 ; CHECK-THUMBv5-NEXT:    .p2align 2
 ; CHECK-THUMBv5-NEXT:  @ %bb.1:
 ; CHECK-THUMBv5-NEXT:  .LCPI4_0:
-; CHECK-THUMBv5-NEXT:    .long 4278255360 @ 0xff00ff00
+; CHECK-THUMBv5-NEXT:    .long 16711935 @ 0xff00ff
 ;
 ; CHECK-ARMv6-LABEL: load_i64_by_i8_bswap:
 ; CHECK-ARMv6:       @ %bb.0:
@@ -495,9 +494,9 @@ define i32 @load_i32_by_i8_nonzero_offset_bswap(ptr %arg) {
 ; CHECK-LABEL: load_i32_by_i8_nonzero_offset_bswap:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    ldr r0, [r0, #1]
+; CHECK-NEXT:    mvn r2, #65280
 ; CHECK-NEXT:    eor r1, r0, r0, ror #16
-; CHECK-NEXT:    bic r1, r1, #16711680
-; CHECK-NEXT:    lsr r1, r1, #8
+; CHECK-NEXT:    and r1, r2, r1, lsr #8
 ; CHECK-NEXT:    eor r0, r1, r0, ror #8
 ; CHECK-NEXT:    mov pc, lr
 ;
@@ -509,17 +508,17 @@ define i32 @load_i32_by_i8_nonzero_offset_bswap(ptr %arg) {
 ; CHECK-THUMBv5-NEXT:    movs r2, r0
 ; CHECK-THUMBv5-NEXT:    rors r2, r1
 ; CHECK-THUMBv5-NEXT:    eors r2, r0
-; CHECK-THUMBv5-NEXT:    ldr r1, .LCPI7_0
-; CHECK-THUMBv5-NEXT:    ands r1, r2
-; CHECK-THUMBv5-NEXT:    lsrs r1, r1, #8
-; CHECK-THUMBv5-NEXT:    movs r2, #8
-; CHECK-THUMBv5-NEXT:    rors r0, r2
-; CHECK-THUMBv5-NEXT:    eors r0, r1
+; CHECK-THUMBv5-NEXT:    lsrs r1, r2, #8
+; CHECK-THUMBv5-NEXT:    ldr r2, .LCPI7_0
+; CHECK-THUMBv5-NEXT:    ands r2, r1
+; CHECK-THUMBv5-NEXT:    movs r1, #8
+; CHECK-THUMBv5-NEXT:    rors r0, r1
+; CHECK-THUMBv5-NEXT:    eors r0, r2
 ; CHECK-THUMBv5-NEXT:    bx lr
 ; CHECK-THUMBv5-NEXT:    .p2align 2
 ; CHECK-THUMBv5-NEXT:  @ %bb.1:
 ; CHECK-THUMBv5-NEXT:  .LCPI7_0:
-; CHECK-THUMBv5-NEXT:    .long 4278255360 @ 0xff00ff00
+; CHECK-THUMBv5-NEXT:    .long 16711935 @ 0xff00ff
 ;
 ; CHECK-ARMv6-LABEL: load_i32_by_i8_nonzero_offset_bswap:
 ; CHECK-ARMv6:       @ %bb.0:
@@ -568,9 +567,9 @@ define i32 @load_i32_by_i8_neg_offset_bswap(ptr %arg) {
 ; CHECK-LABEL: load_i32_by_i8_neg_offset_bswap:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    ldr r0, [r0, #-4]
+; CHECK-NEXT:    mvn r2, #65280
 ; CHECK-NEXT:    eor r1, r0, r0, ror #16
-; CHECK-NEXT:    bic r1, r1, #16711680
-; CHECK-NEXT:    lsr r1, r1, #8
+; CHECK-NEXT:    and r1, r2, r1, lsr #8
 ; CHECK-NEXT:    eor r0, r1, r0, ror #8
 ; CHECK-NEXT:    mov pc, lr
 ;
@@ -585,15 +584,15 @@ define i32 @load_i32_by_i8_neg_offset_bswap(ptr %arg) {
 ; CHECK-THUMBv5-NEXT:    movs r3, r0
 ; CHECK-THUMBv5-NEXT:    rors r3, r1
 ; CHECK-THUMBv5-NEXT:    eors r3, r0
+; CHECK-THUMBv5-NEXT:    lsrs r1, r3, #8
 ; CHECK-THUMBv5-NEXT:    ldr r0, .LCPI8_0
-; CHECK-THUMBv5-NEXT:    ands r0, r3
-; CHECK-THUMBv5-NEXT:    lsrs r0, r0, #8
+; CHECK-THUMBv5-NEXT:    ands r0, r1
 ; CHECK-THUMBv5-NEXT:    eors r0, r2
 ; CHECK-THUMBv5-NEXT:    bx lr
 ; CHECK-THUMBv5-NEXT:    .p2align 2
 ; CHECK-THUMBv5-NEXT:  @ %bb.1:
 ; CHECK-THUMBv5-NEXT:  .LCPI8_0:
-; CHECK-THUMBv5-NEXT:    .long 4278255360 @ 0xff00ff00
+; CHECK-THUMBv5-NEXT:    .long 16711935 @ 0xff00ff
 ;
 ; CHECK-ARMv6-LABEL: load_i32_by_i8_neg_offset_bswap:
 ; CHECK-ARMv6:       @ %bb.0:
@@ -644,9 +643,9 @@ define i32 @load_i32_by_bswap_i16(ptr %arg) {
 ; CHECK-LABEL: load_i32_by_bswap_i16:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    ldr r0, [r0]
+; CHECK-NEXT:    mvn r2, #65280
 ; CHECK-NEXT:    eor r1, r0, r0, ror #16
-; CHECK-NEXT:    bic r1, r1, #16711680
-; CHECK-NEXT:    lsr r1, r1, #8
+; CHECK-NEXT:    and r1, r2, r1, lsr #8
 ; CHECK-NEXT:    eor r0, r1, r0, ror #8
 ; CHECK-NEXT:    mov pc, lr
 ;
@@ -660,15 +659,15 @@ define i32 @load_i32_by_bswap_i16(ptr %arg) {
 ; CHECK-THUMBv5-NEXT:    movs r3, r0
 ; CHECK-THUMBv5-NEXT:    rors r3, r1
 ; CHECK-THUMBv5-NEXT:    eors r3, r0
+; CHECK-THUMBv5-NEXT:    lsrs r1, r3, #8
 ; CHECK-THUMBv5-NEXT:    ldr r0, .LCPI9_0
-; CHECK-THUMBv5-NEXT:    ands r0, r3
-; CHECK-THUMBv5-NEXT:    lsrs r0, r0, #8
+; CHECK-THUMBv5-NEXT:    ands r0, r1
 ; CHECK-THUMBv5-NEXT:    eors r0, r2
 ; CHECK-THUMBv5-NEXT:    bx lr
 ; CHECK-THUMBv5-NEXT:    .p2align 2
 ; CHECK-THUMBv5-NEXT:  @ %bb.1:
 ; CHECK-THUMBv5-NEXT:  .LCPI9_0:
-; CHECK-THUMBv5-NEXT:    .long 4278255360 @ 0xff00ff00
+; CHECK-THUMBv5-NEXT:    .long 16711935 @ 0xff00ff
 ;
 ; CHECK-ARMv6-LABEL: load_i32_by_bswap_i16:
 ; CHECK-ARMv6:       @ %bb.0:
