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s390x: map saturating truncation to a packs/packu
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‎llvm/lib/Target/SystemZ/SystemZInstrVector.td‎

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Original file line numberDiff line numberDiff line change
@@ -1299,6 +1299,46 @@ let Predicates = [FeatureVectorEnhancements3] in {
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(VMNLQ VR128:$x, VR128:$y)>;
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}
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// Instantiate packs/packu: recognize a saturating truncation and convert
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// into the corresponding packs/packu instruction.
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multiclass SignedSaturatingTruncate<ValueType input, ValueType output,
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Instruction packs> {
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def : Pat<
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(output (z_pack
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(smin (smax (input VR128:$a), ssat_trunc_min_vec), ssat_trunc_max_vec),
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(smin (smax (input VR128:$b), ssat_trunc_min_vec), ssat_trunc_max_vec)
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)),
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(packs VR128:$a, VR128:$b)
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>;
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def : Pat<
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(output (z_pack
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(smax (smin (input VR128:$a), ssat_trunc_max_vec), ssat_trunc_min_vec),
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(smax (smin (input VR128:$b), ssat_trunc_max_vec), ssat_trunc_min_vec)
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)),
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(packs VR128:$a, VR128:$b)
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>;
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}
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defm : SignedSaturatingTruncate<v8i16, v16i8, VPKSH>;
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defm : SignedSaturatingTruncate<v4i32, v8i16, VPKSF>;
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defm : SignedSaturatingTruncate<v2i64, v4i32, VPKSG>;
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multiclass UnsignedSaturatingTruncate<ValueType input, ValueType output,
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Instruction packu> {
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def : Pat<
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(output (z_pack
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(umin (input VR128:$a), usat_trunc_max_vec),
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(umin (input VR128:$b), usat_trunc_max_vec)
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)),
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(packu VR128:$a, VR128:$b)
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>;
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}
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defm : UnsignedSaturatingTruncate<v8i16, v16i8, VPKLSH>;
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defm : UnsignedSaturatingTruncate<v4i32, v8i16, VPKLSF>;
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defm : UnsignedSaturatingTruncate<v2i64, v4i32, VPKLSG>;
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// Instantiate comparison patterns to recognize VACC/VSCBI for TYPE.
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multiclass IntegerComputeCarryOrBorrow<ValueType type,
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Instruction vacc, Instruction vscbi> {

‎llvm/lib/Target/SystemZ/SystemZOperators.td‎

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Original file line numberDiff line numberDiff line change
@@ -1067,6 +1067,31 @@ def vsplat_imm_eq_1 : PatFrag<(ops), (build_vector), [{
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}]>;
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def z_vzext1 : PatFrag<(ops node:$x), (and node:$x, vsplat_imm_eq_1)>;
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// Vector constants for saturating truncation, containing the minimum and
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// maximum value for the integer type that is half of the element width.
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def ssat_trunc_min_vec: PatFrag<(ops), (build_vector), [{
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APInt Imm;
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EVT EltTy = N->getValueType(0).getVectorElementType();
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unsigned SizeInBits = EltTy.getSizeInBits();
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APInt min = APInt::getSignedMinValue(SizeInBits / 2).sext(SizeInBits);
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return ISD::isConstantSplatVector(N, Imm) && APInt::isSameValue(Imm, min);
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}]>;
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def ssat_trunc_max_vec: PatFrag<(ops), (build_vector), [{
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APInt Imm;
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EVT EltTy = N->getValueType(0).getVectorElementType();
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unsigned SizeInBits = EltTy.getSizeInBits();
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APInt max = APInt::getSignedMaxValue(SizeInBits / 2).sext(SizeInBits);
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return ISD::isConstantSplatVector(N, Imm) && APInt::isSameValue(Imm, max);
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}]>;
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def usat_trunc_max_vec: PatFrag<(ops), (build_vector), [{
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APInt Imm;
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EVT EltTy = N->getValueType(0).getVectorElementType();
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unsigned SizeInBits = EltTy.getSizeInBits();
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APInt max = APInt::getMaxValue(SizeInBits / 2).zext(SizeInBits);
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return ISD::isConstantSplatVector(N, Imm) && APInt::isSameValue(Imm, max);
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}]>;
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// Signed "integer greater than zero" on vectors.
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def z_vicmph_zero : PatFrag<(ops node:$x), (z_vicmph node:$x, immAllZerosV)>;
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‎llvm/test/CodeGen/SystemZ/saturating-truncation.ll‎

Lines changed: 95 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,95 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
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declare <8 x i32> @llvm.smin.v8i32(<8 x i32>, <8 x i32>) #2
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declare <8 x i32> @llvm.smax.v8i32(<8 x i32>, <8 x i32>) #2
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define <16 x i8> @i16_signed(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: i16_signed:
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; CHECK: # %bb.0: # %bb2
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; CHECK-NEXT: vpksh %v24, %v24, %v26
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; CHECK-NEXT: br %r14
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bb2:
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%0 = shufflevector <8 x i16> %a, <8 x i16> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%1 = tail call <16 x i16> @llvm.smax.v16i16(<16 x i16> %0, <16 x i16> splat (i16 -128))
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%2 = tail call <16 x i16> @llvm.smin.v16i16(<16 x i16> %1, <16 x i16> splat (i16 127))
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%3 = trunc nsw <16 x i16> %2 to <16 x i8>
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ret <16 x i8> %3
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ret <16 x i8> %3
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}
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define <8 x i16> @i32_signed(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: i32_signed:
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; CHECK: # %bb.0: # %bb2
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; CHECK-NEXT: vpksf %v24, %v24, %v26
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; CHECK-NEXT: br %r14
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bb2:
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%0 = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%1 = tail call <8 x i32> @llvm.smax.v8i32(<8 x i32> %0, <8 x i32> splat (i32 -32768))
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%2 = tail call <8 x i32> @llvm.smin.v8i32(<8 x i32> %1, <8 x i32> splat (i32 32767))
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%3 = trunc nsw <8 x i32> %2 to <8 x i16>
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ret <8 x i16> %3
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}
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define <4 x i32> @i64_signed(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: i64_signed:
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; CHECK: # %bb.0: # %bb2
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; CHECK-NEXT: vpksg %v24, %v24, %v26
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; CHECK-NEXT: br %r14
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bb2:
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%0 = shufflevector <2 x i64> %a, <2 x i64> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%1 = tail call <4 x i64> @llvm.smax.v4i64(<4 x i64> %0, <4 x i64> splat (i64 -2147483648))
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%2 = tail call <4 x i64> @llvm.smin.v4i64(<4 x i64> %1, <4 x i64> splat (i64 2147483647))
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%3 = trunc nsw <4 x i64> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define <4 x i32> @i64_signed_flipped(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: i64_signed_flipped:
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; CHECK: # %bb.0: # %bb2
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; CHECK-NEXT: vpksg %v24, %v24, %v26
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; CHECK-NEXT: br %r14
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bb2:
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%0 = shufflevector <2 x i64> %a, <2 x i64> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%1 = tail call <4 x i64> @llvm.smin.v4i64(<4 x i64> splat (i64 2147483647), <4 x i64> %0)
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%2 = tail call <4 x i64> @llvm.smax.v4i64(<4 x i64> splat (i64 -2147483648), <4 x i64> %1)
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%3 = trunc nsw <4 x i64> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define <16 x i8> @i16_unsigned(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: i16_unsigned:
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; CHECK: # %bb.0: # %bb2
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; CHECK-NEXT: vpklsh %v24, %v24, %v26
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; CHECK-NEXT: br %r14
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bb2:
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%0 = shufflevector <8 x i16> %a, <8 x i16> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%1 = tail call <16 x i16> @llvm.umin.v16i16(<16 x i16> %0, <16 x i16> splat (i16 255))
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%2 = trunc nuw <16 x i16> %1 to <16 x i8>
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ret <16 x i8> %2
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}
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define <8 x i16> @i32_unsigned(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: i32_unsigned:
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; CHECK: # %bb.0: # %bb2
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; CHECK-NEXT: vpklsf %v24, %v24, %v26
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; CHECK-NEXT: br %r14
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bb2:
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%0 = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%1 = tail call <8 x i32> @llvm.umin.v8i32(<8 x i32> %0, <8 x i32> splat (i32 65535))
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%2 = trunc nsw <8 x i32> %1 to <8 x i16>
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ret <8 x i16> %2
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}
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define <4 x i32> @i64_unsigned(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: i64_unsigned:
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; CHECK: # %bb.0: # %bb2
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; CHECK-NEXT: vpklsg %v24, %v24, %v26
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; CHECK-NEXT: br %r14
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bb2:
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%0 = shufflevector <2 x i64> %a, <2 x i64> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%1 = tail call <4 x i64> @llvm.umin.v4i64(<4 x i64> %0, <4 x i64> splat (i64 4294967295))
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%2 = trunc nuw <4 x i64> %1 to <4 x i32>
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ret <4 x i32> %2
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}

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