Skip to content

Commit 657d189

Browse files
committed
Remove AddedComplexity
1 parent 653c167 commit 657d189

File tree

1 file changed

+24
-27
lines changed

1 file changed

+24
-27
lines changed

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

Lines changed: 24 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1693,40 +1693,37 @@ defm SIMD_RELAXED_FMAX :
16931693
RelaxedBinary<F64x2, int_wasm_relaxed_max, "relaxed_max", 0x110>;
16941694

16951695
// Transform standard fminimum/fmaximum to relaxed versions
1696-
// AddedComplexity ensures these patterns match before the standard MIN/MAX
1697-
let AddedComplexity = 1 in {
1698-
def : Pat<(v4f32 (fminnum (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
1699-
(SIMD_RELAXED_FMIN_F32x4 V128:$lhs, V128:$rhs)>,
1700-
Requires<[HasRelaxedSIMD]>;
1696+
def : Pat<(v4f32 (fminnum (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
1697+
(SIMD_RELAXED_FMIN_F32x4 V128:$lhs, V128:$rhs)>,
1698+
Requires<[HasRelaxedSIMD]>;
17011699

1702-
def : Pat<(v4f32 (fminimumnum (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
1703-
(SIMD_RELAXED_FMIN_F32x4 V128:$lhs, V128:$rhs)>,
1704-
Requires<[HasRelaxedSIMD]>;
1700+
def : Pat<(v4f32 (fminimumnum (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
1701+
(SIMD_RELAXED_FMIN_F32x4 V128:$lhs, V128:$rhs)>,
1702+
Requires<[HasRelaxedSIMD]>;
17051703

1706-
def : Pat<(v4f32 (fmaxnum (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
1707-
(SIMD_RELAXED_FMAX_F32x4 V128:$lhs, V128:$rhs)>,
1708-
Requires<[HasRelaxedSIMD]>;
1704+
def : Pat<(v4f32 (fmaxnum (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
1705+
(SIMD_RELAXED_FMAX_F32x4 V128:$lhs, V128:$rhs)>,
1706+
Requires<[HasRelaxedSIMD]>;
17091707

1710-
def : Pat<(v4f32 (fmaximumnum (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
1711-
(SIMD_RELAXED_FMAX_F32x4 V128:$lhs, V128:$rhs)>,
1712-
Requires<[HasRelaxedSIMD]>;
1708+
def : Pat<(v4f32 (fmaximumnum (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
1709+
(SIMD_RELAXED_FMAX_F32x4 V128:$lhs, V128:$rhs)>,
1710+
Requires<[HasRelaxedSIMD]>;
17131711

1714-
def : Pat<(v2f64 (fminnum (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
1715-
(SIMD_RELAXED_FMIN_F64x2 V128:$lhs, V128:$rhs)>,
1716-
Requires<[HasRelaxedSIMD]>;
1712+
def : Pat<(v2f64 (fminnum (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
1713+
(SIMD_RELAXED_FMIN_F64x2 V128:$lhs, V128:$rhs)>,
1714+
Requires<[HasRelaxedSIMD]>;
17171715

1718-
def : Pat<(v2f64 (fminimumnum (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
1719-
(SIMD_RELAXED_FMIN_F64x2 V128:$lhs, V128:$rhs)>,
1720-
Requires<[HasRelaxedSIMD]>;
1716+
def : Pat<(v2f64 (fminimumnum (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
1717+
(SIMD_RELAXED_FMIN_F64x2 V128:$lhs, V128:$rhs)>,
1718+
Requires<[HasRelaxedSIMD]>;
17211719

1722-
def : Pat<(v2f64 (fmaxnum (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
1723-
(SIMD_RELAXED_FMAX_F64x2 V128:$lhs, V128:$rhs)>,
1724-
Requires<[HasRelaxedSIMD]>;
1720+
def : Pat<(v2f64 (fmaxnum (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
1721+
(SIMD_RELAXED_FMAX_F64x2 V128:$lhs, V128:$rhs)>,
1722+
Requires<[HasRelaxedSIMD]>;
17251723

1726-
def : Pat<(v2f64 (fmaximumnum (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
1727-
(SIMD_RELAXED_FMAX_F64x2 V128:$lhs, V128:$rhs)>,
1728-
Requires<[HasRelaxedSIMD]>;
1729-
}
1724+
def : Pat<(v2f64 (fmaximumnum (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
1725+
(SIMD_RELAXED_FMAX_F64x2 V128:$lhs, V128:$rhs)>,
1726+
Requires<[HasRelaxedSIMD]>;
17301727

17311728
//===----------------------------------------------------------------------===//
17321729
// Relaxed rounding q15 multiplication

0 commit comments

Comments
 (0)