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5 files changed

+80
-262
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‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp‎

Lines changed: 9 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -5934,22 +5934,16 @@ bool CombinerHelper::matchTruncSSatS(MachineInstr &MI,
59345934
unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
59355935
assert(NumSrcBits > NumDstBits && "Unexpected types for truncate operation");
59365936

5937-
APInt MinConst, MaxConst;
59385937
APInt SignedMax = APInt::getSignedMaxValue(NumDstBits).sext(NumSrcBits);
59395938
APInt SignedMin = APInt::getSignedMinValue(NumDstBits).sext(NumSrcBits);
5940-
59415939
if (isLegal({TargetOpcode::G_TRUNC_SSAT_S, {DstTy, SrcTy}})) {
59425940
if (mi_match(Src, MRI,
5943-
m_GSMin(m_GSMax(m_Reg(MatchInfo), m_ICstOrSplat(MinConst)),
5944-
m_ICstOrSplat(MaxConst))) &&
5945-
APInt::isSameValue(MinConst, SignedMin) &&
5946-
APInt::isSameValue(MaxConst, SignedMax))
5941+
m_GSMin(m_GSMax(m_Reg(MatchInfo), m_SpecificICstOrSplat(SignedMin)),
5942+
m_SpecificICstOrSplat(SignedMax))))
59475943
return true;
59485944
if (mi_match(Src, MRI,
5949-
m_GSMax(m_GSMin(m_Reg(MatchInfo), m_ICstOrSplat(MaxConst)),
5950-
m_ICstOrSplat(MinConst))) &&
5951-
APInt::isSameValue(MinConst, SignedMin) &&
5952-
APInt::isSameValue(MaxConst, SignedMax))
5945+
m_GSMax(m_GSMin(m_Reg(MatchInfo), m_SpecificICstOrSplat(SignedMax)),
5946+
m_SpecificICstOrSplat(SignedMin))))
59535947
return true;
59545948
}
59555949
return false;
@@ -5972,24 +5966,19 @@ bool CombinerHelper::matchTruncSSatU(MachineInstr &MI,
59725966
unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
59735967
assert(NumSrcBits > NumDstBits && "Unexpected types for truncate operation");
59745968

5975-
APInt MaxConst;
59765969
APInt UnsignedMax = APInt::getMaxValue(NumDstBits).zext(NumSrcBits);
5977-
59785970
if (isLegal({TargetOpcode::G_TRUNC_SSAT_U, {DstTy, SrcTy}})) {
59795971
if (mi_match(Src, MRI,
59805972
m_GSMin(m_GSMax(m_Reg(MatchInfo), m_SpecificICstOrSplat(0)),
5981-
m_ICstOrSplat(MaxConst))) &&
5982-
APInt::isSameValue(MaxConst, UnsignedMax))
5973+
m_SpecificICstOrSplat(UnsignedMax))))
59835974
return true;
59845975
if (mi_match(Src, MRI,
5985-
m_GSMax(m_GSMin(m_Reg(MatchInfo), m_ICstOrSplat(MaxConst)),
5986-
m_SpecificICstOrSplat(0))) &&
5987-
APInt::isSameValue(MaxConst, UnsignedMax))
5976+
m_GSMax(m_GSMin(m_Reg(MatchInfo), m_SpecificICstOrSplat(UnsignedMax)),
5977+
m_SpecificICstOrSplat(0))))
59885978
return true;
59895979
if (mi_match(Src, MRI,
59905980
m_GUMin(m_GSMax(m_Reg(MatchInfo), m_SpecificICstOrSplat(0)),
5991-
m_ICstOrSplat(MaxConst))) &&
5992-
APInt::isSameValue(MaxConst, UnsignedMax))
5981+
m_SpecificICstOrSplat(UnsignedMax))))
59935982
return true;
59945983
}
59955984
return false;
@@ -6012,13 +6001,10 @@ bool CombinerHelper::matchTruncUSatU(MachineInstr &MI,
60126001
unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
60136002
assert(NumSrcBits > NumDstBits && "Unexpected types for truncate operation");
60146003

6015-
APInt MaxConst;
60166004
APInt UnsignedMax = APInt::getMaxValue(NumDstBits).zext(NumSrcBits);
6017-
60186005
if (isLegal({TargetOpcode::G_TRUNC_SSAT_U, {DstTy, SrcTy}})) {
60196006
if (mi_match(Src, MRI,
6020-
m_GUMin(m_Reg(MatchInfo), m_ICstOrSplat(MaxConst))) &&
6021-
APInt::isSameValue(MaxConst, UnsignedMax))
6007+
m_GUMin(m_Reg(MatchInfo), m_SpecificICstOrSplat(UnsignedMax))))
60226008
return true;
60236009
}
60246010
return false;

‎llvm/lib/Target/AArch64/AArch64Combine.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -367,5 +367,5 @@ def AArch64PostLegalizerCombiner
367367
select_to_minmax, or_to_bsp, combine_concat_vector,
368368
commute_constant_to_rhs, extract_vec_elt_combines,
369369
push_freeze_to_prevent_poison_from_propagating,
370-
combine_mul_cmlt, combine_use_vector_truncate, extmultomull]> {
370+
combine_mul_cmlt, combine_use_vector_truncate, extmultomull, truncsat_combines]> {
371371
}

‎llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll‎

Lines changed: 35 additions & 92 deletions
Original file line numberDiff line numberDiff line change
@@ -1837,21 +1837,11 @@ define <4 x i13> @test_signed_v4f32_v4i13(<4 x float> %f) {
18371837
}
18381838

18391839
define <4 x i16> @test_signed_v4f32_v4i16(<4 x float> %f) {
1840-
; CHECK-SD-LABEL: test_signed_v4f32_v4i16:
1841-
; CHECK-SD: // %bb.0:
1842-
; CHECK-SD-NEXT: fcvtzs v0.4s, v0.4s
1843-
; CHECK-SD-NEXT: sqxtn v0.4h, v0.4s
1844-
; CHECK-SD-NEXT: ret
1845-
;
1846-
; CHECK-GI-LABEL: test_signed_v4f32_v4i16:
1847-
; CHECK-GI: // %bb.0:
1848-
; CHECK-GI-NEXT: movi v1.4s, #127, msl #8
1849-
; CHECK-GI-NEXT: fcvtzs v0.4s, v0.4s
1850-
; CHECK-GI-NEXT: smin v0.4s, v0.4s, v1.4s
1851-
; CHECK-GI-NEXT: mvni v1.4s, #127, msl #8
1852-
; CHECK-GI-NEXT: smax v0.4s, v0.4s, v1.4s
1853-
; CHECK-GI-NEXT: xtn v0.4h, v0.4s
1854-
; CHECK-GI-NEXT: ret
1840+
; CHECK-LABEL: test_signed_v4f32_v4i16:
1841+
; CHECK: // %bb.0:
1842+
; CHECK-NEXT: fcvtzs v0.4s, v0.4s
1843+
; CHECK-NEXT: sqxtn v0.4h, v0.4s
1844+
; CHECK-NEXT: ret
18551845
%x = call <4 x i16> @llvm.fptosi.sat.v4f32.v4i16(<4 x float> %f)
18561846
ret <4 x i16> %x
18571847
}
@@ -2964,12 +2954,8 @@ define <4 x i16> @test_signed_v4f16_v4i16(<4 x half> %f) {
29642954
; CHECK-GI-CVT-LABEL: test_signed_v4f16_v4i16:
29652955
; CHECK-GI-CVT: // %bb.0:
29662956
; CHECK-GI-CVT-NEXT: fcvtl v0.4s, v0.4h
2967-
; CHECK-GI-CVT-NEXT: movi v1.4s, #127, msl #8
29682957
; CHECK-GI-CVT-NEXT: fcvtzs v0.4s, v0.4s
2969-
; CHECK-GI-CVT-NEXT: smin v0.4s, v0.4s, v1.4s
2970-
; CHECK-GI-CVT-NEXT: mvni v1.4s, #127, msl #8
2971-
; CHECK-GI-CVT-NEXT: smax v0.4s, v0.4s, v1.4s
2972-
; CHECK-GI-CVT-NEXT: xtn v0.4h, v0.4s
2958+
; CHECK-GI-CVT-NEXT: sqxtn v0.4h, v0.4s
29732959
; CHECK-GI-CVT-NEXT: ret
29742960
%x = call <4 x i16> @llvm.fptosi.sat.v4f16.v4i16(<4 x half> %f)
29752961
ret <4 x i16> %x
@@ -3513,12 +3499,8 @@ define <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) {
35133499
;
35143500
; CHECK-GI-FP16-LABEL: test_signed_v8f16_v8i8:
35153501
; CHECK-GI-FP16: // %bb.0:
3516-
; CHECK-GI-FP16-NEXT: movi v1.8h, #127
35173502
; CHECK-GI-FP16-NEXT: fcvtzs v0.8h, v0.8h
3518-
; CHECK-GI-FP16-NEXT: mvni v2.8h, #127
3519-
; CHECK-GI-FP16-NEXT: smin v0.8h, v0.8h, v1.8h
3520-
; CHECK-GI-FP16-NEXT: smax v0.8h, v0.8h, v2.8h
3521-
; CHECK-GI-FP16-NEXT: xtn v0.8b, v0.8h
3503+
; CHECK-GI-FP16-NEXT: sqxtn v0.8b, v0.8h
35223504
; CHECK-GI-FP16-NEXT: ret
35233505
%x = call <8 x i8> @llvm.fptosi.sat.v8f16.v8i8(<8 x half> %f)
35243506
ret <8 x i8> %x
@@ -3585,17 +3567,12 @@ define <8 x i16> @test_signed_v8f16_v8i16(<8 x half> %f) {
35853567
;
35863568
; CHECK-GI-CVT-LABEL: test_signed_v8f16_v8i16:
35873569
; CHECK-GI-CVT: // %bb.0:
3588-
; CHECK-GI-CVT-NEXT: fcvtl v2.4s, v0.4h
3570+
; CHECK-GI-CVT-NEXT: fcvtl v1.4s, v0.4h
35893571
; CHECK-GI-CVT-NEXT: fcvtl2 v0.4s, v0.8h
3590-
; CHECK-GI-CVT-NEXT: movi v1.4s, #127, msl #8
3591-
; CHECK-GI-CVT-NEXT: fcvtzs v2.4s, v2.4s
3592-
; CHECK-GI-CVT-NEXT: fcvtzs v0.4s, v0.4s
3593-
; CHECK-GI-CVT-NEXT: smin v2.4s, v2.4s, v1.4s
3594-
; CHECK-GI-CVT-NEXT: smin v0.4s, v0.4s, v1.4s
3595-
; CHECK-GI-CVT-NEXT: mvni v1.4s, #127, msl #8
3596-
; CHECK-GI-CVT-NEXT: smax v2.4s, v2.4s, v1.4s
3597-
; CHECK-GI-CVT-NEXT: smax v0.4s, v0.4s, v1.4s
3598-
; CHECK-GI-CVT-NEXT: uzp1 v0.8h, v2.8h, v0.8h
3572+
; CHECK-GI-CVT-NEXT: fcvtzs v1.4s, v1.4s
3573+
; CHECK-GI-CVT-NEXT: fcvtzs v2.4s, v0.4s
3574+
; CHECK-GI-CVT-NEXT: sqxtn v0.4h, v1.4s
3575+
; CHECK-GI-CVT-NEXT: sqxtn2 v0.8h, v2.4s
35993576
; CHECK-GI-CVT-NEXT: ret
36003577
%x = call <8 x i16> @llvm.fptosi.sat.v8f16.v8i16(<8 x half> %f)
36013578
ret <8 x i16> %x
@@ -4430,26 +4407,13 @@ define <16 x i8> @test_signed_v16f32_v16i8(<16 x float> %f) {
44304407
}
44314408

44324409
define <8 x i16> @test_signed_v8f32_v8i16(<8 x float> %f) {
4433-
; CHECK-SD-LABEL: test_signed_v8f32_v8i16:
4434-
; CHECK-SD: // %bb.0:
4435-
; CHECK-SD-NEXT: fcvtzs v0.4s, v0.4s
4436-
; CHECK-SD-NEXT: fcvtzs v1.4s, v1.4s
4437-
; CHECK-SD-NEXT: sqxtn v0.4h, v0.4s
4438-
; CHECK-SD-NEXT: sqxtn2 v0.8h, v1.4s
4439-
; CHECK-SD-NEXT: ret
4440-
;
4441-
; CHECK-GI-LABEL: test_signed_v8f32_v8i16:
4442-
; CHECK-GI: // %bb.0:
4443-
; CHECK-GI-NEXT: movi v2.4s, #127, msl #8
4444-
; CHECK-GI-NEXT: fcvtzs v0.4s, v0.4s
4445-
; CHECK-GI-NEXT: fcvtzs v1.4s, v1.4s
4446-
; CHECK-GI-NEXT: smin v0.4s, v0.4s, v2.4s
4447-
; CHECK-GI-NEXT: smin v1.4s, v1.4s, v2.4s
4448-
; CHECK-GI-NEXT: mvni v2.4s, #127, msl #8
4449-
; CHECK-GI-NEXT: smax v0.4s, v0.4s, v2.4s
4450-
; CHECK-GI-NEXT: smax v1.4s, v1.4s, v2.4s
4451-
; CHECK-GI-NEXT: uzp1 v0.8h, v0.8h, v1.8h
4452-
; CHECK-GI-NEXT: ret
4410+
; CHECK-LABEL: test_signed_v8f32_v8i16:
4411+
; CHECK: // %bb.0:
4412+
; CHECK-NEXT: fcvtzs v0.4s, v0.4s
4413+
; CHECK-NEXT: fcvtzs v1.4s, v1.4s
4414+
; CHECK-NEXT: sqxtn v0.4h, v0.4s
4415+
; CHECK-NEXT: sqxtn2 v0.8h, v1.4s
4416+
; CHECK-NEXT: ret
44534417
%x = call <8 x i16> @llvm.fptosi.sat.v8f32.v8i16(<8 x float> %f)
44544418
ret <8 x i16> %x
44554419
}
@@ -4469,22 +4433,14 @@ define <16 x i16> @test_signed_v16f32_v16i16(<16 x float> %f) {
44694433
;
44704434
; CHECK-GI-LABEL: test_signed_v16f32_v16i16:
44714435
; CHECK-GI: // %bb.0:
4472-
; CHECK-GI-NEXT: movi v4.4s, #127, msl #8
44734436
; CHECK-GI-NEXT: fcvtzs v0.4s, v0.4s
4474-
; CHECK-GI-NEXT: fcvtzs v1.4s, v1.4s
44754437
; CHECK-GI-NEXT: fcvtzs v2.4s, v2.4s
4438+
; CHECK-GI-NEXT: fcvtzs v4.4s, v1.4s
44764439
; CHECK-GI-NEXT: fcvtzs v3.4s, v3.4s
4477-
; CHECK-GI-NEXT: mvni v5.4s, #127, msl #8
4478-
; CHECK-GI-NEXT: smin v0.4s, v0.4s, v4.4s
4479-
; CHECK-GI-NEXT: smin v1.4s, v1.4s, v4.4s
4480-
; CHECK-GI-NEXT: smin v2.4s, v2.4s, v4.4s
4481-
; CHECK-GI-NEXT: smin v3.4s, v3.4s, v4.4s
4482-
; CHECK-GI-NEXT: smax v0.4s, v0.4s, v5.4s
4483-
; CHECK-GI-NEXT: smax v1.4s, v1.4s, v5.4s
4484-
; CHECK-GI-NEXT: smax v2.4s, v2.4s, v5.4s
4485-
; CHECK-GI-NEXT: smax v3.4s, v3.4s, v5.4s
4486-
; CHECK-GI-NEXT: uzp1 v0.8h, v0.8h, v1.8h
4487-
; CHECK-GI-NEXT: uzp1 v1.8h, v2.8h, v3.8h
4440+
; CHECK-GI-NEXT: sqxtn v0.4h, v0.4s
4441+
; CHECK-GI-NEXT: sqxtn v1.4h, v2.4s
4442+
; CHECK-GI-NEXT: sqxtn2 v0.8h, v4.4s
4443+
; CHECK-GI-NEXT: sqxtn2 v1.8h, v3.4s
44884444
; CHECK-GI-NEXT: ret
44894445
%x = call <16 x i16> @llvm.fptosi.sat.v16f32.v16i16(<16 x float> %f)
44904446
ret <16 x i16> %x
@@ -4553,15 +4509,10 @@ define <16 x i8> @test_signed_v16f16_v16i8(<16 x half> %f) {
45534509
;
45544510
; CHECK-GI-FP16-LABEL: test_signed_v16f16_v16i8:
45554511
; CHECK-GI-FP16: // %bb.0:
4556-
; CHECK-GI-FP16-NEXT: movi v2.8h, #127
45574512
; CHECK-GI-FP16-NEXT: fcvtzs v0.8h, v0.8h
45584513
; CHECK-GI-FP16-NEXT: fcvtzs v1.8h, v1.8h
4559-
; CHECK-GI-FP16-NEXT: mvni v3.8h, #127
4560-
; CHECK-GI-FP16-NEXT: smin v0.8h, v0.8h, v2.8h
4561-
; CHECK-GI-FP16-NEXT: smin v1.8h, v1.8h, v2.8h
4562-
; CHECK-GI-FP16-NEXT: smax v0.8h, v0.8h, v3.8h
4563-
; CHECK-GI-FP16-NEXT: smax v1.8h, v1.8h, v3.8h
4564-
; CHECK-GI-FP16-NEXT: uzp1 v0.16b, v0.16b, v1.16b
4514+
; CHECK-GI-FP16-NEXT: sqxtn v0.8b, v0.8h
4515+
; CHECK-GI-FP16-NEXT: sqxtn2 v0.16b, v1.8h
45654516
; CHECK-GI-FP16-NEXT: ret
45664517
%x = call <16 x i8> @llvm.fptosi.sat.v16f16.v16i8(<16 x half> %f)
45674518
ret <16 x i8> %x
@@ -4592,26 +4543,18 @@ define <16 x i16> @test_signed_v16f16_v16i16(<16 x half> %f) {
45924543
;
45934544
; CHECK-GI-CVT-LABEL: test_signed_v16f16_v16i16:
45944545
; CHECK-GI-CVT: // %bb.0:
4595-
; CHECK-GI-CVT-NEXT: fcvtl v3.4s, v0.4h
4546+
; CHECK-GI-CVT-NEXT: fcvtl v2.4s, v0.4h
4547+
; CHECK-GI-CVT-NEXT: fcvtl v3.4s, v1.4h
45964548
; CHECK-GI-CVT-NEXT: fcvtl2 v0.4s, v0.8h
4597-
; CHECK-GI-CVT-NEXT: fcvtl v4.4s, v1.4h
45984549
; CHECK-GI-CVT-NEXT: fcvtl2 v1.4s, v1.8h
4599-
; CHECK-GI-CVT-NEXT: movi v2.4s, #127, msl #8
4600-
; CHECK-GI-CVT-NEXT: mvni v5.4s, #127, msl #8
4550+
; CHECK-GI-CVT-NEXT: fcvtzs v2.4s, v2.4s
46014551
; CHECK-GI-CVT-NEXT: fcvtzs v3.4s, v3.4s
4602-
; CHECK-GI-CVT-NEXT: fcvtzs v0.4s, v0.4s
4603-
; CHECK-GI-CVT-NEXT: fcvtzs v4.4s, v4.4s
4604-
; CHECK-GI-CVT-NEXT: fcvtzs v1.4s, v1.4s
4605-
; CHECK-GI-CVT-NEXT: smin v3.4s, v3.4s, v2.4s
4606-
; CHECK-GI-CVT-NEXT: smin v0.4s, v0.4s, v2.4s
4607-
; CHECK-GI-CVT-NEXT: smin v4.4s, v4.4s, v2.4s
4608-
; CHECK-GI-CVT-NEXT: smin v1.4s, v1.4s, v2.4s
4609-
; CHECK-GI-CVT-NEXT: smax v2.4s, v3.4s, v5.4s
4610-
; CHECK-GI-CVT-NEXT: smax v0.4s, v0.4s, v5.4s
4611-
; CHECK-GI-CVT-NEXT: smax v3.4s, v4.4s, v5.4s
4612-
; CHECK-GI-CVT-NEXT: smax v1.4s, v1.4s, v5.4s
4613-
; CHECK-GI-CVT-NEXT: uzp1 v0.8h, v2.8h, v0.8h
4614-
; CHECK-GI-CVT-NEXT: uzp1 v1.8h, v3.8h, v1.8h
4552+
; CHECK-GI-CVT-NEXT: fcvtzs v4.4s, v0.4s
4553+
; CHECK-GI-CVT-NEXT: fcvtzs v5.4s, v1.4s
4554+
; CHECK-GI-CVT-NEXT: sqxtn v0.4h, v2.4s
4555+
; CHECK-GI-CVT-NEXT: sqxtn v1.4h, v3.4s
4556+
; CHECK-GI-CVT-NEXT: sqxtn2 v0.8h, v4.4s
4557+
; CHECK-GI-CVT-NEXT: sqxtn2 v1.8h, v5.4s
46154558
; CHECK-GI-CVT-NEXT: ret
46164559
%x = call <16 x i16> @llvm.fptosi.sat.v16f16.v16i16(<16 x half> %f)
46174560
ret <16 x i16> %x

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