update tests

Author: rez5427

llvm/test/CodeGen/AMDGPU/addrspacecast.ll

@@ -17,12 +17,22 @@ entry:
 }
 
 define i64 @test_s_bitreplicate_constant_zero() {
+; GFX11-LABEL: test_s_bitreplicate_constant_zero:
+; GFX11:       ; %bb.0: ; %entry
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %br = call i64 @llvm.amdgcn.s.bitreplicate(i32 0)
   ret i64 %br
 }
 
 define i64 @test_s_bitreplicate_constant_neg_one() {
+; GFX11-LABEL: test_s_bitreplicate_constant_neg_one:
+; GFX11:       ; %bb.0: ; %entry
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_dual_mov_b32 v0, -1 :: v_dual_mov_b32 v1, -1
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %br = call i64 @llvm.amdgcn.s.bitreplicate(i32 -1)
   ret i64 %br

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitreplicate.ll

@@ -0,0 +1,18 @@
+// Make sure that llvm-objdump --mcpu=v3 enables ALU32 feature.
+//
+// Only test a few instructions here, assembler-disassembler.s is more
+// comprehensive but uses --mattr=+alu32 option.
+//
+// RUN: llvm-mc -triple bpfel --mcpu=v3 --assemble --filetype=obj %s -o %t
+// RUN: llvm-objdump -d --mcpu=v2 %t | FileCheck %s --check-prefix=V2
+// RUN: llvm-objdump -d --mcpu=v3 %t | FileCheck %s --check-prefix=V3
+
+w0 = *(u32 *)(r1 + 0)
+lock *(u32 *)(r1 + 0x1) &= w2
+
+
+// V2: 61 10 00 00 00 00 00 00  r0 = *(u32 *)(r1 + 0x0)
+// V2: c3 21 01 00 50 00 00 00  <unknown>
+
+// V3: 61 10 00 00 00 00 00 00  w0 = *(u32 *)(r1 + 0x0)
+// V3: c3 21 01 00 50 00 00 00  lock *(u32 *)(r1 + 0x1) &= w2

llvm/test/CodeGen/BPF/disassemble-mcpu-v3.s

@@ -5,7 +5,7 @@
 ; CHECK-LABEL: test_inlineasm_w_input_constraint
 define dso_local i32 @test_inlineasm_w_input_constraint() {
   tail call void asm sideeffect "w0 = $0", "w"(i32 42)
-; CHECK: w0 = w1
+; CHECK: w0 = w0
   ret i32 42
 }