addressing review comments

Author: himadhith

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

@@ -19208,9 +19208,17 @@ static SDValue combineADDToMAT_PCREL_ADDR(SDNode *N, SelectionDAG &DAG,
   return MatPCRel;
 }
 
+// Transform (add X, (build_vector (T 1), (T 1), ...)) -> (sub X, (XXLEQVOnes))
+// XXLEQVOnes creates an all-1s vector (0xFFFFFFFF...) efficiently via xxleqv
+// Mathematical identity: X + 1 = X - (-1)
+// Applies to v4i32, v2i64, v8i16, v16i8 where all elements are constant 1
+// Requirement: VSX feature for efficient xxleqv generation
 static SDValue combineADDToSUB(SDNode *N, SelectionDAG &DAG,
                                const PPCSubtarget &Subtarget) {
+
   EVT VT = N->getValueType(0);
+  if (!Subtarget.hasVSX())
+    return SDValue();
 
   // Handle v2i64, v4i32, v8i16 and v16i8 types
   if (!(VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v4i32 ||
@@ -19221,10 +19229,6 @@ static SDValue combineADDToSUB(SDNode *N, SelectionDAG &DAG,
   SDValue RHS = N->getOperand(1);
 
   // Check if RHS is BUILD_VECTOR
-  // To satisfy commutative property a+b = b+a
-  if (RHS.getOpcode() != ISD::BUILD_VECTOR)
-    std::swap(LHS, RHS);
-
   if (RHS.getOpcode() != ISD::BUILD_VECTOR)
     return SDValue();
 
@@ -19243,7 +19247,7 @@ static SDValue combineADDToSUB(SDNode *N, SelectionDAG &DAG,
 
   // Bitcast to the target vector type
   SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT, AllOnesVec);
-
+  
   return DAG.getNode(ISD::SUB, DL, VT, LHS, Bitcast);
 }
 

llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll

@@ -25,7 +25,7 @@ define <2 x i64> @increment_by_one(<2 x i64> %x) nounwind {
 ; NOVSX-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
 ; NOVSX-NEXT:    addi 3, 3, .LCPI1_0@toc@l
 ; NOVSX-NEXT:    lvx 3, 0, 3
-; NOVSX-NEXT:    vsubudm 2, 2, 3
+; NOVSX-NEXT:    vaddudm 2, 2, 3
 ; NOVSX-NEXT:    blr
   %result = add <2 x i64> %x, <i64 1, i64 1>
   ret <2 x i64> %result