[AArch64][GlobalISel] Updated test checks

Author: JoshdRod

llvm/test/CodeGen/AArch64/arm64-int-neon.ll

@@ -3,15 +3,7 @@
 ; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel -global-isel-abort=2 -mattr=+fprcvt,+fullfp16 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
 
 
-; CHECK-GI:       warning: Instruction selection used fallback path for test_sqrshl_s32
-; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_sqrshl_s64
-; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_sqshl_s32
-; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_sqshl_s64
-; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_uqrshl_s32
-; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_uqrshl_s64
-; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_uqshl_s32
-; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_uqshl_s64
-; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_uqadd_s32
+; CHECK-GI:  warning: Instruction selection used fallback path for test_uqadd_s32
 ; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_uqadd_s64
 ; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_uqsub_s32
 ; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_uqsub_s64
@@ -236,3 +228,5 @@ define i64 @test_sqdmulls_scalar(float %A){
   %prod = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32  %cvt, i32  %cvt)
   ret i64 %prod
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-GI: {{.*}}

llvm/test/CodeGen/AArch64/arm64-vshift.ll

@@ -142,23 +142,13 @@ define <1 x i64> @sqshl1d_constant(ptr %A) nounwind {
 }
 
 define i64 @sqshl_scalar(ptr %A, ptr %B) nounwind {
-; CHECK-SD-LABEL: sqshl_scalar:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    ldr x8, [x0]
-; CHECK-SD-NEXT:    ldr x9, [x1]
-; CHECK-SD-NEXT:    fmov d0, x8
-; CHECK-SD-NEXT:    fmov d1, x9
-; CHECK-SD-NEXT:    sqshl d0, d0, d1
-; CHECK-SD-NEXT:    fmov x0, d0
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: sqshl_scalar:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    ldr d0, [x0]
-; CHECK-GI-NEXT:    ldr d1, [x1]
-; CHECK-GI-NEXT:    sqshl d0, d0, d1
-; CHECK-GI-NEXT:    fmov x0, d0
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: sqshl_scalar:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr d0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    sqshl d0, d0, d1
+; CHECK-NEXT:    fmov x0, d0
+; CHECK-NEXT:    ret
   %tmp1 = load i64, ptr %A
   %tmp2 = load i64, ptr %B
   %tmp3 = call i64 @llvm.aarch64.neon.sqshl.i64(i64 %tmp1, i64 %tmp2)
@@ -362,23 +352,13 @@ define <1 x i64> @uqshl1d_constant(ptr %A) nounwind {
 }
 
 define i64 @uqshl_scalar(ptr %A, ptr %B) nounwind {
-; CHECK-SD-LABEL: uqshl_scalar:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    ldr x8, [x0]
-; CHECK-SD-NEXT:    ldr x9, [x1]
-; CHECK-SD-NEXT:    fmov d0, x8
-; CHECK-SD-NEXT:    fmov d1, x9
-; CHECK-SD-NEXT:    uqshl d0, d0, d1
-; CHECK-SD-NEXT:    fmov x0, d0
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: uqshl_scalar:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    ldr d0, [x0]
-; CHECK-GI-NEXT:    ldr d1, [x1]
-; CHECK-GI-NEXT:    uqshl d0, d0, d1
-; CHECK-GI-NEXT:    fmov x0, d0
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: uqshl_scalar:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr d0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    uqshl d0, d0, d1
+; CHECK-NEXT:    fmov x0, d0
+; CHECK-NEXT:    ret
   %tmp1 = load i64, ptr %A
   %tmp2 = load i64, ptr %B
   %tmp3 = call i64 @llvm.aarch64.neon.uqshl.i64(i64 %tmp1, i64 %tmp2)
@@ -938,23 +918,13 @@ define <1 x i64> @sqrshl1d_constant(ptr %A) nounwind {
 }
 
 define i64 @sqrshl_scalar(ptr %A, ptr %B) nounwind {
-; CHECK-SD-LABEL: sqrshl_scalar:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    ldr x8, [x0]
-; CHECK-SD-NEXT:    ldr x9, [x1]
-; CHECK-SD-NEXT:    fmov d0, x8
-; CHECK-SD-NEXT:    fmov d1, x9
-; CHECK-SD-NEXT:    sqrshl d0, d0, d1
-; CHECK-SD-NEXT:    fmov x0, d0
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: sqrshl_scalar:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    ldr d0, [x0]
-; CHECK-GI-NEXT:    ldr d1, [x1]
-; CHECK-GI-NEXT:    sqrshl d0, d0, d1
-; CHECK-GI-NEXT:    fmov x0, d0
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: sqrshl_scalar:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr d0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    sqrshl d0, d0, d1
+; CHECK-NEXT:    fmov x0, d0
+; CHECK-NEXT:    ret
   %tmp1 = load i64, ptr %A
   %tmp2 = load i64, ptr %B
   %tmp3 = call i64 @llvm.aarch64.neon.sqrshl.i64(i64 %tmp1, i64 %tmp2)
@@ -964,10 +934,9 @@ define i64 @sqrshl_scalar(ptr %A, ptr %B) nounwind {
 define i64 @sqrshl_scalar_constant(ptr %A) nounwind {
 ; CHECK-SD-LABEL: sqrshl_scalar_constant:
 ; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    ldr x9, [x0]
-; CHECK-SD-NEXT:    mov w8, #1 // =0x1
+; CHECK-SD-NEXT:    mov x8, #1 // =0x1
+; CHECK-SD-NEXT:    ldr d0, [x0]
 ; CHECK-SD-NEXT:    fmov d1, x8
-; CHECK-SD-NEXT:    fmov d0, x9
 ; CHECK-SD-NEXT:    sqrshl d0, d0, d1
 ; CHECK-SD-NEXT:    fmov x0, d0
 ; CHECK-SD-NEXT:    ret
@@ -1064,23 +1033,13 @@ define <1 x i64> @uqrshl1d_constant(ptr %A) nounwind {
 }
 
 define i64 @uqrshl_scalar(ptr %A, ptr %B) nounwind {
-; CHECK-SD-LABEL: uqrshl_scalar:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    ldr x8, [x0]
-; CHECK-SD-NEXT:    ldr x9, [x1]
-; CHECK-SD-NEXT:    fmov d0, x8
-; CHECK-SD-NEXT:    fmov d1, x9
-; CHECK-SD-NEXT:    uqrshl d0, d0, d1
-; CHECK-SD-NEXT:    fmov x0, d0
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: uqrshl_scalar:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    ldr d0, [x0]
-; CHECK-GI-NEXT:    ldr d1, [x1]
-; CHECK-GI-NEXT:    uqrshl d0, d0, d1
-; CHECK-GI-NEXT:    fmov x0, d0
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: uqrshl_scalar:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr d0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    uqrshl d0, d0, d1
+; CHECK-NEXT:    fmov x0, d0
+; CHECK-NEXT:    ret
   %tmp1 = load i64, ptr %A
   %tmp2 = load i64, ptr %B
   %tmp3 = call i64 @llvm.aarch64.neon.uqrshl.i64(i64 %tmp1, i64 %tmp2)
@@ -1090,10 +1049,9 @@ define i64 @uqrshl_scalar(ptr %A, ptr %B) nounwind {
 define i64 @uqrshl_scalar_constant(ptr %A) nounwind {
 ; CHECK-SD-LABEL: uqrshl_scalar_constant:
 ; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    ldr x9, [x0]
-; CHECK-SD-NEXT:    mov w8, #1 // =0x1
+; CHECK-SD-NEXT:    mov x8, #1 // =0x1
+; CHECK-SD-NEXT:    ldr d0, [x0]
 ; CHECK-SD-NEXT:    fmov d1, x8
-; CHECK-SD-NEXT:    fmov d0, x9
 ; CHECK-SD-NEXT:    uqrshl d0, d0, d1
 ; CHECK-SD-NEXT:    fmov x0, d0
 ; CHECK-SD-NEXT:    ret
@@ -2746,6 +2704,7 @@ define <4 x i32> @neon_sshl4s_wrong_ext_constant_shift(ptr %A) nounwind {
 ; CHECK-GI-NEXT:    ret
   %tmp1 = load <4 x i8>, ptr %A
   %tmp2 = sext <4 x i8> %tmp1 to <4 x i32>
+  %tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
   ret <4 x i32> %tmp3
 }