Fully use inreg to generate scalar shl

Signed-off-by: John Lu <[email protected]>

Author: LU-JOHN

llvm/test/CodeGen/AMDGPU/shl64_reduce.ll

@@ -147,62 +147,80 @@ define <4 x i64> @shl_v4_or16(<4 x i64> %arg0, <4 x i64> %shift_amt) {
   ret <4 x i64> %shl
 }
 
-; test inreg
+; test SGPR
 
-define i64 @shl_or16_inreg(i64 %arg0, i64 inreg %shift_amt) {
-; CHECK-LABEL: shl_or16_inreg:
+define i64 @shl_or16_sgpr(i64 inreg %arg0, i64 inreg %shift_amt) {
+; CHECK-LABEL: shl_or16_sgpr:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    s_or_b32 s4, s16, 16
-; CHECK-NEXT:    v_lshlrev_b64 v[0:1], s4, v[0:1]
+; CHECK-NEXT:    s_or_b32 s4, s18, 16
+; CHECK-NEXT:    s_lshl_b64 s[4:5], s[16:17], s4
+; CHECK-NEXT:    v_mov_b32_e32 v0, s4
+; CHECK-NEXT:    v_mov_b32_e32 v1, s5
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %or = or i64 %shift_amt, 16
   %shl = shl i64 %arg0, %or
   ret i64 %shl
 }
 
-define <2 x i64> @shl_v2_or16_inreg(<2 x i64> %arg0, <2 x i64> inreg %shift_amt) {
-; CHECK-LABEL: shl_v2_or16_inreg:
+define <2 x i64> @shl_v2_or16_sgpr(<2 x i64> inreg %arg0, <2 x i64> inreg %shift_amt) {
+; CHECK-LABEL: shl_v2_or16_sgpr:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    s_or_b32 s4, s18, 16
-; CHECK-NEXT:    s_or_b32 s5, s16, 16
-; CHECK-NEXT:    v_lshlrev_b64 v[0:1], s5, v[0:1]
-; CHECK-NEXT:    v_lshlrev_b64 v[2:3], s4, v[2:3]
+; CHECK-NEXT:    s_or_b32 s6, s22, 16
+; CHECK-NEXT:    s_or_b32 s4, s20, 16
+; CHECK-NEXT:    s_lshl_b64 s[4:5], s[16:17], s4
+; CHECK-NEXT:    s_lshl_b64 s[6:7], s[18:19], s6
+; CHECK-NEXT:    v_mov_b32_e32 v0, s4
+; CHECK-NEXT:    v_mov_b32_e32 v1, s5
+; CHECK-NEXT:    v_mov_b32_e32 v2, s6
+; CHECK-NEXT:    v_mov_b32_e32 v3, s7
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %or = or <2 x i64> %shift_amt, splat (i64 16)
   %shl = shl <2 x i64> %arg0, %or
   ret <2 x i64> %shl
 }
 
-define <3 x i64> @shl_v3_or16_inreg(<3 x i64> %arg0, <3 x i64> inreg %shift_amt) {
-; CHECK-LABEL: shl_v3_or16_inreg:
+define <3 x i64> @shl_v3_or16_sgpr(<3 x i64> inreg %arg0, <3 x i64> inreg %shift_amt) {
+; CHECK-LABEL: shl_v3_or16_sgpr:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    s_or_b32 s4, s20, 16
-; CHECK-NEXT:    s_or_b32 s5, s18, 16
-; CHECK-NEXT:    s_or_b32 s6, s16, 16
-; CHECK-NEXT:    v_lshlrev_b64 v[0:1], s6, v[0:1]
-; CHECK-NEXT:    v_lshlrev_b64 v[2:3], s5, v[2:3]
-; CHECK-NEXT:    v_lshlrev_b64 v[4:5], s4, v[4:5]
+; CHECK-NEXT:    s_or_b32 s8, s26, 16
+; CHECK-NEXT:    s_or_b32 s6, s24, 16
+; CHECK-NEXT:    s_or_b32 s4, s22, 16
+; CHECK-NEXT:    s_lshl_b64 s[4:5], s[16:17], s4
+; CHECK-NEXT:    s_lshl_b64 s[6:7], s[18:19], s6
+; CHECK-NEXT:    s_lshl_b64 s[8:9], s[20:21], s8
+; CHECK-NEXT:    v_mov_b32_e32 v0, s4
+; CHECK-NEXT:    v_mov_b32_e32 v1, s5
+; CHECK-NEXT:    v_mov_b32_e32 v2, s6
+; CHECK-NEXT:    v_mov_b32_e32 v3, s7
+; CHECK-NEXT:    v_mov_b32_e32 v4, s8
+; CHECK-NEXT:    v_mov_b32_e32 v5, s9
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %or = or <3 x i64> %shift_amt, splat (i64 16)
   %shl = shl <3 x i64> %arg0, %or
   ret <3 x i64> %shl
 }
 
-define <4 x i64> @shl_v4_or16_inreg(<4 x i64> %arg0, <4 x i64> inreg %shift_amt) {
-; CHECK-LABEL: shl_v4_or16_inreg:
+define <4 x i64> @shl_v4_or16_sgpr(<4 x i64> inreg %arg0, <4 x i64> inreg %shift_amt) {
+; CHECK-LABEL: shl_v4_or16_sgpr:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    s_or_b32 s4, s22, 16
-; CHECK-NEXT:    s_or_b32 s5, s20, 16
-; CHECK-NEXT:    s_or_b32 s6, s18, 16
-; CHECK-NEXT:    s_or_b32 s7, s16, 16
-; CHECK-NEXT:    v_lshlrev_b64 v[0:1], s7, v[0:1]
-; CHECK-NEXT:    v_lshlrev_b64 v[2:3], s6, v[2:3]
-; CHECK-NEXT:    v_lshlrev_b64 v[4:5], s5, v[4:5]
-; CHECK-NEXT:    v_lshlrev_b64 v[6:7], s4, v[6:7]
+; CHECK-NEXT:    v_or_b32_e32 v0, 16, v0
+; CHECK-NEXT:    s_or_b32 s8, s28, 16
+; CHECK-NEXT:    s_or_b32 s6, s26, 16
+; CHECK-NEXT:    s_or_b32 s4, s24, 16
+; CHECK-NEXT:    s_lshl_b64 s[4:5], s[16:17], s4
+; CHECK-NEXT:    s_lshl_b64 s[6:7], s[18:19], s6
+; CHECK-NEXT:    s_lshl_b64 s[8:9], s[20:21], s8
+; CHECK-NEXT:    v_lshlrev_b64 v[6:7], v0, s[22:23]
+; CHECK-NEXT:    v_mov_b32_e32 v0, s4
+; CHECK-NEXT:    v_mov_b32_e32 v1, s5
+; CHECK-NEXT:    v_mov_b32_e32 v2, s6
+; CHECK-NEXT:    v_mov_b32_e32 v3, s7
+; CHECK-NEXT:    v_mov_b32_e32 v4, s8
+; CHECK-NEXT:    v_mov_b32_e32 v5, s9
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %or = or <4 x i64> %shift_amt, splat (i64 16)
   %shl = shl <4 x i64> %arg0, %or
@@ -276,61 +294,70 @@ define <4 x i64> @shl_v4_or32(<4 x i64> %arg0, <4 x i64> %shift_amt) {
   ret <4 x i64> %shl
 }
 
-; test inreg
+; test SGPR
 
-define i64 @shl_or32_inreg(i64 %arg0, i64 inreg %shift_amt) {
-; CHECK-LABEL: shl_or32_inreg:
+define i64 @shl_or32_sgpr(i64 inreg %arg0, i64 inreg %shift_amt) {
+; CHECK-LABEL: shl_or32_sgpr:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_lshlrev_b32_e32 v1, s16, v0
+; CHECK-NEXT:    s_lshl_b32 s4, s16, s18
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 0
+; CHECK-NEXT:    v_mov_b32_e32 v1, s4
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %or = or i64 %shift_amt, 32
   %shl = shl i64 %arg0, %or
   ret i64 %shl
 }
 
-define <2 x i64> @shl_v2_or32_inreg(<2 x i64> %arg0, <2 x i64> inreg %shift_amt) {
-; CHECK-LABEL: shl_v2_or32_inreg:
+define <2 x i64> @shl_v2_or32_sgpr(<2 x i64> inreg %arg0, <2 x i64> inreg %shift_amt) {
+; CHECK-LABEL: shl_v2_or32_sgpr:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_lshlrev_b32_e32 v1, s16, v0
-; CHECK-NEXT:    v_lshlrev_b32_e32 v3, s18, v2
+; CHECK-NEXT:    s_lshl_b32 s4, s16, s20
+; CHECK-NEXT:    s_lshl_b32 s5, s18, s22
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 0
+; CHECK-NEXT:    v_mov_b32_e32 v1, s4
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 0
+; CHECK-NEXT:    v_mov_b32_e32 v3, s5
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %or = or <2 x i64> %shift_amt, splat (i64 32)
   %shl = shl <2 x i64> %arg0, %or
   ret <2 x i64> %shl
 }
 
-define <3 x i64> @shl_v3_or32_inreg(<3 x i64> %arg0, <3 x i64> inreg %shift_amt) {
-; CHECK-LABEL: shl_v3_or32_inreg:
+define <3 x i64> @shl_v3_or32_sgpr(<3 x i64> inreg %arg0, <3 x i64> inreg %shift_amt) {
+; CHECK-LABEL: shl_v3_or32_sgpr:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_lshlrev_b32_e32 v1, s16, v0
-; CHECK-NEXT:    v_lshlrev_b32_e32 v3, s18, v2
-; CHECK-NEXT:    v_lshlrev_b32_e32 v5, s20, v4
+; CHECK-NEXT:    s_lshl_b32 s4, s16, s22
+; CHECK-NEXT:    s_lshl_b32 s5, s18, s24
+; CHECK-NEXT:    s_lshl_b32 s6, s20, s26
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 0
+; CHECK-NEXT:    v_mov_b32_e32 v1, s4
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 0
+; CHECK-NEXT:    v_mov_b32_e32 v3, s5
 ; CHECK-NEXT:    v_mov_b32_e32 v4, 0
+; CHECK-NEXT:    v_mov_b32_e32 v5, s6
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %or = or <3 x i64> %shift_amt, splat (i64 32)
   %shl = shl <3 x i64> %arg0, %or
   ret <3 x i64> %shl
 }
 
-define <4 x i64> @shl_v4_or32_inreg(<4 x i64> %arg0, <4 x i64> inreg %shift_amt) {
-; CHECK-LABEL: shl_v4_or32_inreg:
+define <4 x i64> @shl_v4_or32_sgpr(<4 x i64> inreg %arg0, <4 x i64> inreg %shift_amt) {
+; CHECK-LABEL: shl_v4_or32_sgpr:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_lshlrev_b32_e32 v1, s16, v0
-; CHECK-NEXT:    v_lshlrev_b32_e32 v3, s18, v2
-; CHECK-NEXT:    v_lshlrev_b32_e32 v5, s20, v4
-; CHECK-NEXT:    v_lshlrev_b32_e32 v7, s22, v6
+; CHECK-NEXT:    s_lshl_b32 s4, s16, s24
+; CHECK-NEXT:    s_lshl_b32 s5, s18, s26
+; CHECK-NEXT:    s_lshl_b32 s6, s20, s28
+; CHECK-NEXT:    v_lshlrev_b32_e64 v7, v0, s22
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 0
+; CHECK-NEXT:    v_mov_b32_e32 v1, s4
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 0
+; CHECK-NEXT:    v_mov_b32_e32 v3, s5
 ; CHECK-NEXT:    v_mov_b32_e32 v4, 0
+; CHECK-NEXT:    v_mov_b32_e32 v5, s6
 ; CHECK-NEXT:    v_mov_b32_e32 v6, 0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %or = or <4 x i64> %shift_amt, splat (i64 32)