fixup! [RISCV] Assign different scheduling classes for VMADC/VMSBC

Author: mshockwave

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

@@ -649,24 +649,18 @@ multiclass VALUm_IV_V_X_I<string opcodestr, bits<6> funct6>
 }
 
 multiclass VALUNoVm_IV_V_X<string opcodestr, bits<6> funct6> {
-  // if LSB of funct6 is 1, it's a mask-producing instruction that
-  // uses a different scheduling class.
-  defvar WritePrefix = !if(funct6{0}, "WriteVICALUM", "WriteVICALU");
   def V : VALUVVNoVm<funct6, OPIVV, opcodestr # ".vv">,
-          SchedBinaryMC<WritePrefix#"V", "ReadVICALUV", "ReadVICALUV",
+          SchedBinaryMC<"WriteVICALUMV", "ReadVICALUV", "ReadVICALUV",
                         forceMasked=0>;
   def X : VALUVXNoVm<funct6, OPIVX, opcodestr # ".vx">,
-          SchedBinaryMC<WritePrefix#"X", "ReadVICALUV", "ReadVICALUX",
+          SchedBinaryMC<"WriteVICALUMX", "ReadVICALUV", "ReadVICALUX",
                         forceMasked=0>;
 }
 
 multiclass VALUNoVm_IV_V_X_I<string opcodestr, bits<6> funct6>
    : VALUNoVm_IV_V_X<opcodestr, funct6> {
-  // if LSB of funct6 is 1, it's a mask-producing instruction that
-  // uses a different scheduling class.
-  defvar WriteSched = !if(funct6{0}, "WriteVICALUMI", "WriteVICALUI");
   def I : VALUVINoVm<funct6, opcodestr # ".vi">,
-          SchedUnaryMC<WriteSched, "ReadVICALUV", forceMasked=0>;
+          SchedUnaryMC<"WriteVICALUMI", "ReadVICALUV", forceMasked=0>;
 }
 
 multiclass VALU_FV_F<string opcodestr, bits<6> funct6> {