review comments

Author: Hardcode84

mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp

@@ -1394,6 +1394,7 @@ struct AMDGPUSwizzleBitModeLowering
     unsigned xorMask = op.getXorMask();
 
     // bit 15 is 0 for the BitMode swizzle.
+    // https://gpuopen.com/learn/amd-gcn-assembly-cross-lane-operations/
     unsigned mask = andMask | (orMask << 5) | (xorMask << 10);
     Value maskValue = createI32Constant(rewriter, loc, mask);
     SmallVector<Value> swizzled;

mlir/lib/Conversion/LLVMCommon/Pattern.cpp

@@ -427,7 +427,7 @@ SmallVector<Value> mlir::LLVM::decomposeValue(OpBuilder &builder, Location loc,
   src = builder.create<LLVM::BitcastOp>(loc, vecType, src);
 
   SmallVector<Value> res;
-  for (auto i : llvm::seq<int64_t>(0, numElements)) {
+  for (auto i : llvm::seq(numElements)) {
     Value idx = createI32Constant(builder, loc, i);
     Value elem = builder.create<LLVM::ExtractElementOp>(loc, src, idx);
     res.emplace_back(elem);