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Convert G_FCONSTANT to G_CONSTANT
1 parent 81c6378 commit 7c868d7

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4 files changed

+31
-34
lines changed

4 files changed

+31
-34
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp‎

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -740,16 +740,6 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
740740
const APFloat &FPimm = MI.getOperand(1).getFPImm()->getValueAPF();
741741
APInt Imm = FPimm.bitcastToAPInt();
742742
unsigned Size = MRI->getType(DstReg).getSizeInBits();
743-
744-
if (!Subtarget->hasStdExtF() &&
745-
(Size == 32 || (Size == 64 && Subtarget->is64Bit()))) {
746-
if (!materializeImm(DstReg, Imm.getSExtValue(), MIB))
747-
return false;
748-
749-
MI.eraseFromParent();
750-
return true;
751-
}
752-
753743
if (Size == 16 || Size == 32 || (Size == 64 && Subtarget->is64Bit())) {
754744
Register GPRReg = MRI->createVirtualRegister(&RISCV::GPRRegClass);
755745
if (!materializeImm(GPRReg, Imm.getSExtValue(), MIB))

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp‎

Lines changed: 16 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -871,6 +871,12 @@ bool RISCVLegalizerInfo::shouldBeInConstantPool(const APInt &APImm,
871871
return !(!SeqLo.empty() && (SeqLo.size() + 2) <= STI.getMaxBuildIntsCost());
872872
}
873873

874+
bool RISCVLegalizerInfo::shouldBeInFConstantPool(const APFloat &APImm) const {
875+
if (APImm.isZero() || APImm.isExactlyValue(1.0))
876+
return false;
877+
return true;
878+
}
879+
874880
bool RISCVLegalizerInfo::legalizeVScale(MachineInstr &MI,
875881
MachineIRBuilder &MIB) const {
876882
const LLT XLenTy(STI.getXLenVT());
@@ -1361,12 +1367,16 @@ bool RISCVLegalizerInfo::legalizeCustom(
13611367
case TargetOpcode::G_ABS:
13621368
return Helper.lowerAbsToMaxNeg(MI);
13631369
case TargetOpcode::G_FCONSTANT: {
1364-
const ConstantFP *ConstVal = MI.getOperand(1).getFPImm();
1365-
bool ShouldOptForSize = MF.getFunction().hasOptSize();
1366-
if (!shouldBeInConstantPool(ConstVal->getValue().bitcastToAPInt(),
1367-
ShouldOptForSize))
1368-
return true;
1369-
return Helper.lowerFConstant(MI);
1370+
const APFloat FVal = MI.getOperand(1).getFPImm()->getValueAPF();
1371+
if (shouldBeInFConstantPool(FVal))
1372+
return Helper.lowerFConstant(MI);
1373+
1374+
// Convert G_FCONSTANT to G_CONSTANT.
1375+
Register DstReg = MI.getOperand(0).getReg();
1376+
MIRBuilder.buildConstant(DstReg, FVal.bitcastToAPInt());
1377+
1378+
MI.eraseFromParent();
1379+
return true;
13701380
}
13711381
case TargetOpcode::G_CONSTANT: {
13721382
const Function &F = MF.getFunction();

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@ class RISCVLegalizerInfo : public LegalizerInfo {
3939

4040
private:
4141
bool shouldBeInConstantPool(const APInt &APImm, bool ShouldOptForSize) const;
42+
bool shouldBeInFConstantPool(const APFloat &APImm) const;
4243
bool legalizeShlAshrLshr(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
4344
GISelChangeObserver &Observer) const;
4445

‎llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp‎

Lines changed: 14 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -112,8 +112,7 @@ using namespace llvm;
112112
RISCVRegisterBankInfo::RISCVRegisterBankInfo(unsigned HwMode)
113113
: RISCVGenRegisterBankInfo(HwMode) {}
114114

115-
static const RegisterBankInfo::ValueMapping *
116-
getFPValueMapping(unsigned Size, bool HasFPExt = true) {
115+
static const RegisterBankInfo::ValueMapping *getFPValueMapping(unsigned Size) {
117116
unsigned Idx;
118117
switch (Size) {
119118
default:
@@ -122,10 +121,10 @@ getFPValueMapping(unsigned Size, bool HasFPExt = true) {
122121
Idx = RISCV::FPRB16Idx;
123122
break;
124123
case 32:
125-
Idx = HasFPExt ? RISCV::FPRB32Idx : RISCV::GPRB32Idx;
124+
Idx = RISCV::FPRB32Idx;
126125
break;
127126
case 64:
128-
Idx = HasFPExt ? RISCV::FPRB64Idx : RISCV::GPRB64Idx;
127+
Idx = RISCV::FPRB64Idx;
129128
break;
130129
}
131130
return &RISCV::ValueMappings[Idx];
@@ -220,9 +219,6 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
220219
const TargetSubtargetInfo &STI = MF.getSubtarget();
221220
const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
222221

223-
// D and Zfh extension implies F.
224-
bool HasFPExt = STI.hasFeature(RISCV::FeatureStdExtF);
225-
226222
unsigned GPRSize = getMaximumSize(RISCV::GPRBRegBankID);
227223
assert((GPRSize == 32 || GPRSize == 64) && "Unexpected GPR size");
228224

@@ -270,7 +266,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
270266
if (Ty.isVector())
271267
Mapping = getVRBValueMapping(Size.getKnownMinValue());
272268
else if (isPreISelGenericFloatingPointOpcode(Opc))
273-
Mapping = getFPValueMapping(Size.getFixedValue(), HasFPExt);
269+
Mapping = getFPValueMapping(Size.getFixedValue());
274270
else
275271
Mapping = GPRValueMapping;
276272

@@ -305,7 +301,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
305301
if (DstTy.isVector())
306302
Mapping = getVRBValueMapping(DstMinSize);
307303
else if (anyUseOnlyUseFP(Dst, MRI, TRI))
308-
Mapping = getFPValueMapping(DstMinSize, HasFPExt);
304+
Mapping = getFPValueMapping(DstMinSize);
309305

310306
return getInstructionMapping(DefaultMappingID, /*Cost=*/1, Mapping,
311307
NumOperands);
@@ -343,7 +339,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
343339
// assume this was a floating point load in the IR. If it was
344340
// not, we would have had a bitcast before reaching that
345341
// instruction.
346-
OpdsMapping[0] = getFPValueMapping(Size, HasFPExt);
342+
OpdsMapping[0] = getFPValueMapping(Size);
347343
break;
348344
}
349345

@@ -371,7 +367,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
371367

372368
MachineInstr *DefMI = MRI.getVRegDef(MI.getOperand(0).getReg());
373369
if (onlyDefinesFP(*DefMI, MRI, TRI))
374-
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits(), HasFPExt);
370+
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
375371
break;
376372
}
377373
case TargetOpcode::G_SELECT: {
@@ -436,7 +432,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
436432

437433
const ValueMapping *Mapping = GPRValueMapping;
438434
if (NumFP >= 2)
439-
Mapping = getFPValueMapping(Ty.getSizeInBits(), HasFPExt);
435+
Mapping = getFPValueMapping(Ty.getSizeInBits());
440436

441437
OpdsMapping[0] = OpdsMapping[2] = OpdsMapping[3] = Mapping;
442438
break;
@@ -448,13 +444,13 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
448444
case RISCV::G_FCLASS: {
449445
LLT Ty = MRI.getType(MI.getOperand(1).getReg());
450446
OpdsMapping[0] = GPRValueMapping;
451-
OpdsMapping[1] = getFPValueMapping(Ty.getSizeInBits(), HasFPExt);
447+
OpdsMapping[1] = getFPValueMapping(Ty.getSizeInBits());
452448
break;
453449
}
454450
case TargetOpcode::G_SITOFP:
455451
case TargetOpcode::G_UITOFP: {
456452
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
457-
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits(), HasFPExt);
453+
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
458454
OpdsMapping[1] = GPRValueMapping;
459455
break;
460456
}
@@ -472,7 +468,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
472468
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
473469
if (GPRSize == 32 && Ty.getSizeInBits() == 64) {
474470
assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
475-
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits(), HasFPExt);
471+
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
476472
OpdsMapping[1] = GPRValueMapping;
477473
OpdsMapping[2] = GPRValueMapping;
478474
}
@@ -485,7 +481,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
485481
assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
486482
OpdsMapping[0] = GPRValueMapping;
487483
OpdsMapping[1] = GPRValueMapping;
488-
OpdsMapping[2] = getFPValueMapping(Ty.getSizeInBits(), HasFPExt);
484+
OpdsMapping[2] = getFPValueMapping(Ty.getSizeInBits());
489485
}
490486
break;
491487
}
@@ -499,7 +495,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
499495
if ((GPRSize == 32 && ScalarTy.getSizeInBits() == 64) ||
500496
onlyDefinesFP(*DefMI, MRI, TRI)) {
501497
assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
502-
OpdsMapping[1] = getFPValueMapping(ScalarTy.getSizeInBits(), HasFPExt);
498+
OpdsMapping[1] = getFPValueMapping(ScalarTy.getSizeInBits());
503499
} else
504500
OpdsMapping[1] = GPRValueMapping;
505501
break;
@@ -518,7 +514,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
518514
OpdsMapping[Idx] =
519515
getVRBValueMapping(Ty.getSizeInBits().getKnownMinValue());
520516
else if (isPreISelGenericFloatingPointOpcode(Opc))
521-
OpdsMapping[Idx] = getFPValueMapping(Ty.getSizeInBits(), HasFPExt);
517+
OpdsMapping[Idx] = getFPValueMapping(Ty.getSizeInBits());
522518
else
523519
OpdsMapping[Idx] = GPRValueMapping;
524520
}

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