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Revert back div/rem latencies
Signed-off-by: Mikhail R. Gadelha <[email protected]>
1 parent 7f610b2 commit 7d0a715

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2 files changed

+21
-18
lines changed

2 files changed

+21
-18
lines changed

‎llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,9 +70,12 @@ def : WriteRes<WriteIMul32, [SMX60_IEU]> { let Latency = 3; }
7070
def : WriteRes<WriteIMul, [SMX60_IEU]> { let Latency = 6; }
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7272
// Integer division/remainder
73-
let Latency = 3, ReleaseAtCycles = [3] in {
73+
// Worst case latency is used
74+
let Latency = 12, ReleaseAtCycles = [12] in {
7475
def : WriteRes<WriteIDiv32, [SMX60_IEUA]>;
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def : WriteRes<WriteIRem32, [SMX60_IEUA]>;
77+
}
78+
let Latency = 20, ReleaseAtCycles = [20] in {
7679
def : WriteRes<WriteIDiv, [SMX60_IEUA]>;
7780
def : WriteRes<WriteIRem, [SMX60_IEUA]>;
7881
}

‎llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -233,14 +233,14 @@ bseti a0, a1, 1
233233
# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU MULHU mulhu a0, a0, a0
234234
# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU MULHSU mulhsu a0, a0, a0
235235
# CHECK-NEXT: 1 3 0.50 3 SMX60_IEU MULW mulw a0, a0, a0
236-
# CHECK-NEXT: 1 3 3.00 3 SMX60_IEU[3],SMX60_IEUA[3] DIV div a0, a1, a2
237-
# CHECK-NEXT: 1 3 3.00 3 SMX60_IEU[3],SMX60_IEUA[3] DIVU divu a0, a1, a2
238-
# CHECK-NEXT: 1 3 3.00 3 SMX60_IEU[3],SMX60_IEUA[3] REM rem a0, a1, a2
239-
# CHECK-NEXT: 1 3 3.00 3 SMX60_IEU[3],SMX60_IEUA[3] REMU remu a0, a1, a2
240-
# CHECK-NEXT: 1 3 3.00 3 SMX60_IEU[3],SMX60_IEUA[3] DIVW divw a0, a1, a2
241-
# CHECK-NEXT: 1 3 3.00 3 SMX60_IEU[3],SMX60_IEUA[3] DIVUW divuw a0, a1, a2
242-
# CHECK-NEXT: 1 3 3.00 3 SMX60_IEU[3],SMX60_IEUA[3] REMW remw a0, a1, a2
243-
# CHECK-NEXT: 1 3 3.00 3 SMX60_IEU[3],SMX60_IEUA[3] REMUW remuw a0, a1, a2
236+
# CHECK-NEXT: 1 20 20.00 20 SMX60_IEU[20],SMX60_IEUA[20] DIV div a0, a1, a2
237+
# CHECK-NEXT: 1 20 20.00 20 SMX60_IEU[20],SMX60_IEUA[20] DIVU divu a0, a1, a2
238+
# CHECK-NEXT: 1 20 20.00 20 SMX60_IEU[20],SMX60_IEUA[20] REM rem a0, a1, a2
239+
# CHECK-NEXT: 1 20 20.00 20 SMX60_IEU[20],SMX60_IEUA[20] REMU remu a0, a1, a2
240+
# CHECK-NEXT: 1 12 12.00 12 SMX60_IEU[12],SMX60_IEUA[12] DIVW divw a0, a1, a2
241+
# CHECK-NEXT: 1 12 12.00 12 SMX60_IEU[12],SMX60_IEUA[12] DIVUW divuw a0, a1, a2
242+
# CHECK-NEXT: 1 12 12.00 12 SMX60_IEU[12],SMX60_IEUA[12] REMW remw a0, a1, a2
243+
# CHECK-NEXT: 1 12 12.00 12 SMX60_IEU[12],SMX60_IEUA[12] REMUW remuw a0, a1, a2
244244
# CHECK-NEXT: 1 1 0.50 U 1 SMX60_IEU CSRRW csrrw t0, 4095, t1
245245
# CHECK-NEXT: 1 1 0.50 U 1 SMX60_IEU CSRRS csrrs s3, fflags, s5
246246
# CHECK-NEXT: 1 1 0.50 U 1 SMX60_IEU CSRRC csrrc sp, 0, ra
@@ -301,7 +301,7 @@ bseti a0, a1, 1
301301

302302
# CHECK: Resource pressure per iteration:
303303
# CHECK-NEXT: [0] [1] [2] [3.0] [3.1]
304-
# CHECK-NEXT: - 75.00 43.00 5.50 5.50
304+
# CHECK-NEXT: - 179.00 43.00 5.50 5.50
305305

306306
# CHECK: Resource pressure by instruction:
307307
# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] Instructions:
@@ -360,14 +360,14 @@ bseti a0, a1, 1
360360
# CHECK-NEXT: - 0.50 0.50 - - mulhu a0, a0, a0
361361
# CHECK-NEXT: - 0.50 0.50 - - mulhsu a0, a0, a0
362362
# CHECK-NEXT: - 0.50 0.50 - - mulw a0, a0, a0
363-
# CHECK-NEXT: - 3.00 - - - div a0, a1, a2
364-
# CHECK-NEXT: - 3.00 - - - divu a0, a1, a2
365-
# CHECK-NEXT: - 3.00 - - - rem a0, a1, a2
366-
# CHECK-NEXT: - 3.00 - - - remu a0, a1, a2
367-
# CHECK-NEXT: - 3.00 - - - divw a0, a1, a2
368-
# CHECK-NEXT: - 3.00 - - - divuw a0, a1, a2
369-
# CHECK-NEXT: - 3.00 - - - remw a0, a1, a2
370-
# CHECK-NEXT: - 3.00 - - - remuw a0, a1, a2
363+
# CHECK-NEXT: - 20.00 - - - div a0, a1, a2
364+
# CHECK-NEXT: - 20.00 - - - divu a0, a1, a2
365+
# CHECK-NEXT: - 20.00 - - - rem a0, a1, a2
366+
# CHECK-NEXT: - 20.00 - - - remu a0, a1, a2
367+
# CHECK-NEXT: - 12.00 - - - divw a0, a1, a2
368+
# CHECK-NEXT: - 12.00 - - - divuw a0, a1, a2
369+
# CHECK-NEXT: - 12.00 - - - remw a0, a1, a2
370+
# CHECK-NEXT: - 12.00 - - - remuw a0, a1, a2
371371
# CHECK-NEXT: - 0.50 0.50 - - csrrw t0, 4095, t1
372372
# CHECK-NEXT: - 0.50 0.50 - - csrrs s3, fflags, s5
373373
# CHECK-NEXT: - 0.50 0.50 - - csrrc sp, 0, ra

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