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[llvm][RISCV] Support P Extension CodeGen
This patch supports: PSLLI_B, PSLLI_H, PSLLI_W, PSSLAI_H and PSSLAI_W
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‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -523,6 +523,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::SADDSAT, VTs, Legal);
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setOperationAction(ISD::USUBSAT, VTs, Legal);
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setOperationAction(ISD::SSUBSAT, VTs, Legal);
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setOperationAction(ISD::SSHLSAT, VTs, Legal);
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setOperationAction({ISD::AVGFLOORS, ISD::AVGFLOORU}, VTs, Legal);
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setOperationAction({ISD::ABDS, ISD::ABDU}, VTs, Legal);
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setOperationAction(ISD::BUILD_VECTOR, VTs, Custom);

‎llvm/lib/Target/RISCV/RISCVInstrInfoP.td‎

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@@ -19,6 +19,8 @@
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//===----------------------------------------------------------------------===//
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def simm10 : RISCVSImmOp<10>, TImmLeaf<XLenVT, "return isInt<10>(Imm);">;
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def tuimm3 : RISCVUImmOp<3>, TImmLeaf<XLenVT, "return isUInt<3>(Imm);">;
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def tuimm4 : RISCVUImmOp<4>, TImmLeaf<XLenVT, "return isUInt<4>(Imm);">;
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def SImm8UnsignedAsmOperand : SImmAsmOperand<8, "Unsigned"> {
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let RenderMethod = "addSImm8UnsignedOperands";
@@ -1517,6 +1519,17 @@ let Predicates = [HasStdExtP] in {
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def: Pat<(XLenVecI16VT (abds GPR:$rs1, GPR:$rs2)), (PDIF_H GPR:$rs1, GPR:$rs2)>;
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def: Pat<(XLenVecI16VT (abdu GPR:$rs1, GPR:$rs2)), (PDIFU_H GPR:$rs1, GPR:$rs2)>;
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// 8-bit logical shift left patterns
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def: Pat<(XLenVecI8VT (shl GPR:$rs1, (XLenVecI8VT (riscv_pli tuimm3:$shamt)))),
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(PSLLI_B GPR:$rs1, tuimm3:$shamt)>;
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// 16-bit logical shift left patterns
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def: Pat<(XLenVecI16VT (shl GPR:$rs1, (XLenVecI16VT (riscv_pli tuimm4:$shamt)))),
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(PSLLI_H GPR:$rs1, tuimm4:$shamt)>;
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// 16-bit signed saturation shift left patterns
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def: Pat<(XLenVecI16VT (sshlsat GPR:$rs1, (XLenVecI16VT (riscv_pli tuimm4:$shamt)))),
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(PSSLAI_H GPR:$rs1, tuimm4:$shamt)>;
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// 8-bit PLI SD node pattern
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def: Pat<(XLenVecI8VT (riscv_pli simm8_unsigned:$imm8)), (PLI_B simm8_unsigned:$imm8)>;
@@ -1543,6 +1556,14 @@ let Predicates = [HasStdExtP, IsRV64] in {
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def: Pat<(v2i32 (riscv_pasub GPR:$rs1, GPR:$rs2)), (PASUB_W GPR:$rs1, GPR:$rs2)>;
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def: Pat<(v2i32 (riscv_pasubu GPR:$rs1, GPR:$rs2)), (PASUBU_W GPR:$rs1, GPR:$rs2)>;
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// 32-bit logical shift left patterns
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def: Pat<(v2i32 (shl GPR:$rs1, (v2i32 (riscv_pli tuimm4:$shamt)))),
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(PSLLI_W GPR:$rs1, tuimm4:$shamt)>;
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// 32-bit signed saturation shift left patterns
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def: Pat<(v2i32 (sshlsat GPR:$rs1, (v2i32 (riscv_pli tuimm4:$shamt)))),
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(PSSLAI_W GPR:$rs1, tuimm4:$shamt)>;
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// Load/Store patterns
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def : StPat<store, SD, GPR, v8i8>;
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def : StPat<store, SD, GPR, v4i16>;

‎llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll‎

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Original file line numberDiff line numberDiff line change
@@ -496,6 +496,48 @@ define void @test_extract_vector_8(ptr %ret_ptr, ptr %a_ptr) {
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ret void
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}
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; Test logical shift left immediate for v2i16
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define void @test_pslli_h(ptr %ret_ptr, ptr %a_ptr) {
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; CHECK-LABEL: test_pslli_h:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lw a1, 0(a1)
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; CHECK-NEXT: pslli.h a1, a1, 2
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; CHECK-NEXT: sw a1, 0(a0)
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; CHECK-NEXT: ret
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%a = load <2 x i16>, ptr %a_ptr
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%res = shl <2 x i16> %a, splat(i16 2)
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store <2 x i16> %res, ptr %ret_ptr
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ret void
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}
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; Test logical shift left immediate for v4i8
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define void @test_pslli_b(ptr %ret_ptr, ptr %a_ptr) {
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; CHECK-LABEL: test_pslli_b:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lw a1, 0(a1)
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; CHECK-NEXT: pslli.b a1, a1, 2
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; CHECK-NEXT: sw a1, 0(a0)
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; CHECK-NEXT: ret
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%a = load <4 x i8>, ptr %a_ptr
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%res = shl <4 x i8> %a, splat(i8 2)
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store <4 x i8> %res, ptr %ret_ptr
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ret void
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}
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; Test arithmetic saturation shift left immediate for v2i16
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define void @test_psslai_h(ptr %ret_ptr, ptr %a_ptr) {
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; CHECK-LABEL: test_psslai_h:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lw a1, 0(a1)
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; CHECK-NEXT: psslai.h a1, a1, 2
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; CHECK-NEXT: sw a1, 0(a0)
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; CHECK-NEXT: ret
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%a = load <2 x i16>, ptr %a_ptr
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%res = call <2 x i16> @llvm.sshl.sat.v2i16(<2 x i16> %a, <2 x i16> splat(i16 2))
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store <2 x i16> %res, ptr %ret_ptr
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ret void
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}
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; Intrinsic declarations
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declare <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16>, <2 x i16>)
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declare <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16>, <2 x i16>)
@@ -513,3 +555,4 @@ declare <4 x i8> @llvm.smin.v4i8(<4 x i8>, <4 x i8>)
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declare <4 x i8> @llvm.smax.v4i8(<4 x i8>, <4 x i8>)
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declare <4 x i8> @llvm.umin.v4i8(<4 x i8>, <4 x i8>)
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declare <4 x i8> @llvm.umax.v4i8(<4 x i8>, <4 x i8>)
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declare <2 x i16> @llvm.sshl.sat.v2i16(<2 x i16> %a, <2 x i16> %b)

‎llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll‎

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Original file line numberDiff line numberDiff line change
@@ -495,6 +495,62 @@ define void @test_extract_vector_32(ptr %ret_ptr, ptr %a_ptr) {
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ret void
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}
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; Test logical shift left immediate for v4i16
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define void @test_pslli_h(ptr %ret_ptr, ptr %a_ptr) {
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; CHECK-LABEL: test_pslli_h:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ld a1, 0(a1)
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; CHECK-NEXT: pslli.h a1, a1, 2
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; CHECK-NEXT: sd a1, 0(a0)
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; CHECK-NEXT: ret
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%a = load <4 x i16>, ptr %a_ptr
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%res = shl <4 x i16> %a, splat(i16 2)
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store <4 x i16> %res, ptr %ret_ptr
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ret void
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}
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; Test logical shift left immediate for v8i8
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define void @test_pslli_b(ptr %ret_ptr, ptr %a_ptr) {
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; CHECK-LABEL: test_pslli_b:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ld a1, 0(a1)
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; CHECK-NEXT: pslli.b a1, a1, 2
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; CHECK-NEXT: sd a1, 0(a0)
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; CHECK-NEXT: ret
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%a = load <8 x i8>, ptr %a_ptr
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%res = shl <8 x i8> %a, splat(i8 2)
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store <8 x i8> %res, ptr %ret_ptr
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ret void
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}
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; Test logical shift left immediate for v2i32
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define void @test_pslli_w(ptr %ret_ptr, ptr %a_ptr) {
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; CHECK-LABEL: test_pslli_w:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ld a1, 0(a1)
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; CHECK-NEXT: pslli.w a1, a1, 2
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; CHECK-NEXT: sd a1, 0(a0)
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; CHECK-NEXT: ret
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%a = load <2 x i32>, ptr %a_ptr
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%res = shl <2 x i32> %a, splat(i32 2)
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store <2 x i32> %res, ptr %ret_ptr
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ret void
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}
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; Test arithmetic saturation shift left immediate for v2i32
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define void @test_psslai_w(ptr %ret_ptr, ptr %a_ptr) {
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; CHECK-LABEL: test_psslai_w:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ld a1, 0(a1)
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; CHECK-NEXT: psslai.w a1, a1, 2
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; CHECK-NEXT: sd a1, 0(a0)
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; CHECK-NEXT: ret
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%a = load <2 x i32>, ptr %a_ptr
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%res = call <2 x i32> @llvm.sshl.sat.v2i32(<2 x i32> %a, <2 x i32> splat(i32 2))
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store <2 x i32> %res, ptr %ret_ptr
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ret void
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}
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; Intrinsic declarations
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declare <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16>, <4 x i16>)
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declare <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16>, <4 x i16>)
@@ -512,3 +568,4 @@ declare <8 x i8> @llvm.smin.v8i8(<8 x i8>, <8 x i8>)
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declare <8 x i8> @llvm.smax.v8i8(<8 x i8>, <8 x i8>)
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declare <8 x i8> @llvm.umin.v8i8(<8 x i8>, <8 x i8>)
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declare <8 x i8> @llvm.umax.v8i8(<8 x i8>, <8 x i8>)
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declare <2 x i32> @llvm.sshl.sat.v2i32(<2 x i32> %a, <2 x i32> %b)

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