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1 parent 4917b9c commit 7f89718Copy full SHA for 7f89718
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
@@ -29,6 +29,10 @@ enum { MAX_LANES = 64 };
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using namespace llvm;
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+// TODO -- delete this flag once we have more robust mechanisms to allocate the
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+// optimal RC for Opc and Dest of MFMA. In particular, there are high RP cases
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+// where it is better to produce the VGPR form (e.g. if there are VGPR users
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+// of the MFMA result).
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cl::opt<bool> MFMAVGPRForm(
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"amdgpu-mfma-vgpr-form", cl::Hidden,
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cl::desc("Whether to force use VGPR for Opc and Dest of MFMA. If "
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