Address comments

Author: sunshaoce

llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

@@ -740,24 +740,33 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
     const APFloat &FPimm = MI.getOperand(1).getFPImm()->getValueAPF();
     APInt Imm = FPimm.bitcastToAPInt();
     unsigned Size = MRI->getType(DstReg).getSizeInBits();
+
+    if (!Subtarget->hasStdExtF() &&
+        (Size == 32 || (Size == 64 && Subtarget->is64Bit()))) {
+      // No fp extension, so we need to go through GPRs.
+      Register GPRReg = MRI->createVirtualRegister(&RISCV::GPRRegClass);
+      if (!materializeImm(GPRReg, Imm.getSExtValue(), MIB))
+        return false;
+
+      unsigned Opcode =
+          (Subtarget->is64Bit() && Size == 32) ? RISCV::ADDW : RISCV::ADD;
+      auto MV = MIB.buildInstr(Opcode, {DstReg}, {GPRReg, Register(RISCV::X0)});
+      if (!MV.constrainAllUses(TII, TRI, RBI))
+        return false;
+
+      MI.eraseFromParent();
+      return true;
+    }
+
     if (Size == 16 || Size == 32 || (Size == 64 && Subtarget->is64Bit())) {
       Register GPRReg = MRI->createVirtualRegister(&RISCV::GPRRegClass);
       if (!materializeImm(GPRReg, Imm.getSExtValue(), MIB))
         return false;
 
-      unsigned Opcode = RISCV::INIT_UNDEF;
-      MachineInstrBuilder FMV;
-      if (Subtarget->hasStdExtF() || Subtarget->hasStdExtD() ||
-          Subtarget->hasStdExtZfh()) {
-        Opcode = Size == 64   ? RISCV::FMV_D_X
-                 : Size == 32 ? RISCV::FMV_W_X
-                              : RISCV::FMV_H_X;
-        FMV = MIB.buildInstr(Opcode, {DstReg}, {GPRReg});
-      } else {
-        Opcode =
-            (Subtarget->is64Bit() && Size == 32) ? RISCV::ADDW : RISCV::ADD;
-        FMV = MIB.buildInstr(Opcode, {DstReg}, {GPRReg, Register(RISCV::X0)});
-      }
+      unsigned Opcode = Size == 64   ? RISCV::FMV_D_X
+                        : Size == 32 ? RISCV::FMV_W_X
+                                     : RISCV::FMV_H_X;
+      auto FMV = MIB.buildInstr(Opcode, {DstReg}, {GPRReg});
       if (!FMV.constrainAllUses(TII, TRI, RBI))
         return false;
     } else {

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

@@ -871,12 +871,6 @@ bool RISCVLegalizerInfo::shouldBeInConstantPool(const APInt &APImm,
   return !(!SeqLo.empty() && (SeqLo.size() + 2) <= STI.getMaxBuildIntsCost());
 }
 
-bool RISCVLegalizerInfo::shouldBeInFConstantPool(const APFloat &APImm) const {
-  if (APImm.isZero() || APImm.isExactlyValue(1.0))
-    return false;
-  return true;
-}
-
 bool RISCVLegalizerInfo::legalizeVScale(MachineInstr &MI,
                                         MachineIRBuilder &MIB) const {
   const LLT XLenTy(STI.getXLenVT());
@@ -1368,7 +1362,9 @@ bool RISCVLegalizerInfo::legalizeCustom(
     return Helper.lowerAbsToMaxNeg(MI);
   case TargetOpcode::G_FCONSTANT: {
     const ConstantFP *ConstVal = MI.getOperand(1).getFPImm();
-    if (!shouldBeInFConstantPool(ConstVal->getValue()))
+    bool ShouldOptForSize = MF.getFunction().hasOptSize();
+    if (!shouldBeInConstantPool(ConstVal->getValue().bitcastToAPInt(),
+                                ShouldOptForSize))
       return true;
     return Helper.lowerFConstant(MI);
   }

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h

@@ -39,7 +39,6 @@ class RISCVLegalizerInfo : public LegalizerInfo {
 
 private:
   bool shouldBeInConstantPool(const APInt &APImm, bool ShouldOptForSize) const;
-  bool shouldBeInFConstantPool(const APFloat &APImm) const;
   bool legalizeShlAshrLshr(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
                            GISelChangeObserver &Observer) const;
 

llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

@@ -220,9 +220,8 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   const TargetSubtargetInfo &STI = MF.getSubtarget();
   const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
 
-  bool HasFPExt = STI.hasFeature(RISCV::FeatureStdExtF) ||
-                  STI.hasFeature(RISCV::FeatureStdExtD) ||
-                  STI.hasFeature(RISCV::FeatureStdExtZfh);
+  // D and Zfh extension implies F.
+  bool HasFPExt = STI.hasFeature(RISCV::FeatureStdExtF);
 
   unsigned GPRSize = getMaximumSize(RISCV::GPRBRegBankID);
   assert((GPRSize == 32 || GPRSize == 64) && "Unexpected GPR size");