Skip to content

Commit 84c4f79

Browse files
committed
Additional Changes
Change-Id: If201b1c194b91da0321e3cbe2d3288f1069a06e7
1 parent 9a4f77a commit 84c4f79

File tree

1 file changed

+8
-28
lines changed

1 file changed

+8
-28
lines changed

llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

Lines changed: 8 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -158,25 +158,15 @@ class QCIMVCC<bits<3> funct3, string opcodestr>
158158
}
159159

160160
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
161-
class QCIMVCCI<bits<3> funct3, string opcodestr>
161+
class QCIMVCCI<bits<3> funct3, string opcodestr, DAGOperand immType>
162162
: RVInstR4<0b10, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd),
163-
(ins GPRNoX0:$rs1, simm5:$imm, GPRNoX0:$rs3),
163+
(ins GPRNoX0:$rs1, immType:$imm, GPRNoX0:$rs3),
164164
opcodestr, "$rd, $rs1, $imm, $rs3"> {
165165
bits<5> imm;
166166

167167
let rs2 = imm;
168168
}
169169

170-
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
171-
class QCIMVCCUI<bits<3> funct3, string opcodestr>
172-
: RVInstR4<0b10, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd),
173-
(ins GPRNoX0:$rs1, uimm5:$imm, GPRNoX0:$rs3),
174-
opcodestr, "$rd, $rs1, $imm, $rs3"> {
175-
bits<5> imm;
176-
177-
let rs2 = imm;
178-
}
179-
180170
//===----------------------------------------------------------------------===//
181171
// Instructions
182172
//===----------------------------------------------------------------------===//
@@ -309,28 +299,18 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
309299
}
310300

311301
def QC_MVEQ : QCIMVCC<0b000, "qc.mveq">;
312-
313302
def QC_MVNE : QCIMVCC<0b001, "qc.mvne">;
314-
315303
def QC_MVLT : QCIMVCC<0b100, "qc.mvlt">;
316-
317304
def QC_MVGE : QCIMVCC<0b101, "qc.mvge">;
318-
319305
def QC_MVLTU : QCIMVCC<0b110, "qc.mvltu">;
320-
321306
def QC_MVGEU : QCIMVCC<0b111, "qc.mvgeu">;
322307

323-
def QC_MVEQI : QCIMVCCI <0b000, "qc.mveqi">;
324-
325-
def QC_MVNEI : QCIMVCCI <0b001, "qc.mvnei">;
326-
327-
def QC_MVLTI : QCIMVCCI <0b100, "qc.mvlti">;
328-
329-
def QC_MVGEI : QCIMVCCI <0b101, "qc.mvgei">;
330-
331-
def QC_MVLTUI : QCIMVCCUI<0b110, "qc.mvltui">;
332-
333-
def QC_MVGEUI : QCIMVCCUI<0b111, "qc.mvgeui">;
308+
def QC_MVEQI : QCIMVCCI<0b000, "qc.mveqi", simm5>;
309+
def QC_MVNEI : QCIMVCCI<0b001, "qc.mvnei", simm5>;
310+
def QC_MVLTI : QCIMVCCI<0b100, "qc.mvlti", simm5>;
311+
def QC_MVGEI : QCIMVCCI<0b101, "qc.mvgei", simm5>;
312+
def QC_MVLTUI : QCIMVCCI<0b110, "qc.mvltui", uimm5>;
313+
def QC_MVGEUI : QCIMVCCI<0b111, "qc.mvgeui", uimm5>;
334314
} // Predicates = [HasVendorXqcicm, IsRV32], DecoderNamespace = "Xqcicm"
335315

336316
//===----------------------------------------------------------------------===//

0 commit comments

Comments
 (0)