Remove Redundant Ops

Author: easyonaadit

llvm/include/llvm/IR/IntrinsicsAMDGPU.td

@@ -2343,10 +2343,8 @@ class AMDGPUWaveReduce<LLVMType data_ty = llvm_anyint_ty> : Intrinsic<
     [IntrNoMem, IntrConvergent, IntrWillReturn, IntrNoCallback, IntrNoFree, ImmArg<ArgIndex<1>>]>;
 
 multiclass AMDGPUWaveReduceOps {
-  foreach Op = [
-    "umin", "min", "umax", "max", "uadd", "add", "usub", "sub", "and", "or",
-    "xor"
-  ] in {
+  foreach Op =
+      ["umin", "min", "umax", "max", "add", "sub", "and", "or", "xor"] in {
     def Op : AMDGPUWaveReduce;
   }
 }

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

@@ -5007,9 +5007,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
       break;
     }
     case Intrinsic::amdgcn_wave_reduce_add:
-    case Intrinsic::amdgcn_wave_reduce_uadd:
     case Intrinsic::amdgcn_wave_reduce_sub:
-    case Intrinsic::amdgcn_wave_reduce_usub:
     case Intrinsic::amdgcn_wave_reduce_min:
     case Intrinsic::amdgcn_wave_reduce_umin:
     case Intrinsic::amdgcn_wave_reduce_max:

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

@@ -5097,7 +5097,7 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
 
       bool IsWave32 = ST.isWave32();
       unsigned MovOpc = IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
-      MCRegister ExecReg = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
+      unsigned ExecReg = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
       unsigned CountReg =
           IsWave32 ? AMDGPU::S_BCNT1_I32_B32 : AMDGPU::S_BCNT1_I32_B64;
 
@@ -5262,12 +5262,8 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
     return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_MAX_U32);
   case AMDGPU::WAVE_REDUCE_MAX_PSEUDO_I32:
     return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_MAX_I32);
-  case AMDGPU::WAVE_REDUCE_UADD_PSEUDO_U32:
-    return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_ADD_I32);
   case AMDGPU::WAVE_REDUCE_ADD_PSEUDO_I32:
     return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_ADD_I32);
-  case AMDGPU::WAVE_REDUCE_USUB_PSEUDO_U32:
-    return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_SUB_I32);
   case AMDGPU::WAVE_REDUCE_SUB_PSEUDO_I32:
     return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_SUB_I32);
   case AMDGPU::WAVE_REDUCE_AND_PSEUDO_B32:

llvm/lib/Target/AMDGPU/SIInstructions.td

@@ -306,9 +306,9 @@ def : GCNPat<(i32 (int_amdgcn_set_inactive_chain_arg i32:$src, i32:$inactive)),
 // clang-format off
 defvar int_amdgcn_wave_reduce_ = "int_amdgcn_wave_reduce_";
 multiclass
-    AMDGPUWaveReducePseudoGenerator<string Op, string DataType, string Size> {
+    AMDGPUWaveReducePseudoGenerator<string Op, string DataType> {
   let usesCustomInserter = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC] in {
-    def !toupper(Op) #"_PSEUDO_" #DataType #Size
+    def !toupper(Op) #"_PSEUDO_" #DataType
         : VPseudoInstSI<(outs SGPR_32 : $sdst),
                         (ins VSrc_b32 : $src, VSrc_b32 : $strategy),
                         [(set i32 : $sdst, (!cast<AMDGPUWaveReduce>(int_amdgcn_wave_reduce_ #Op) i32 : $src, i32 : $strategy))]> {}
@@ -317,17 +317,15 @@ multiclass
 // clang-format on
 
 // Input list : [Operation_name,
-//              type - Signed(I)/Unsigned(U)/Float(F)/Bitwise(B),
-//              Size_in_bits]
+//              type - Signed(I)/Unsigned(U)/Float(F)/Bitwise(B)]
 defvar Operations = [
-  ["umin", "U", "32"], ["min", "I", "32"], ["umax", "U", "32"],
-  ["max", "I", "32"], ["uadd", "U", "32"], ["add", "I", "32"],
-  ["usub", "U", "32"], ["sub", "I", "32"], ["and", "B", "32"],
-  ["or", "B", "32"], ["xor", "B", "32"]
+  ["umin", "U32"], ["min", "I32"], ["umax", "U32"], ["max", "I32"],
+  ["add", "I32"], ["sub", "I32"], ["and", "B32"], ["or", "B32"],
+  ["xor", "B32"]
 ];
 
 foreach Op = Operations in {
-  defm WAVE_REDUCE_ : AMDGPUWaveReducePseudoGenerator<Op[0], Op[1], Op[2]>;
+  defm WAVE_REDUCE_ : AMDGPUWaveReducePseudoGenerator<Op[0], Op[1]>;
 }
 
 let usesCustomInserter = 1, Defs = [VCC] in {