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zGoldthorpezGoldthorpe
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Rewrote tests in LLVM IR.
Also added tests for <4 x i2> vectors, which are still within the scope of the patch, particularly because an arithmetic right shift is an identity transformation.
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‎llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll‎

Lines changed: 135 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1881,6 +1881,141 @@ define amdgpu_ps i65 @s_ashr_i65_33(i65 inreg %value) {
18811881
ret i65 %result
18821882
}
18831883

1884+
define <4 x i2> @v_ashr_v4i2(<4 x i2> %value, <4 x i2> %amount) {
1885+
; GFX6-LABEL: v_ashr_v4i2:
1886+
; GFX6: ; %bb.0:
1887+
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1888+
; GFX6-NEXT: v_and_b32_e32 v4, 3, v4
1889+
; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 2
1890+
; GFX6-NEXT: v_ashrrev_i32_e32 v0, v4, v0
1891+
; GFX6-NEXT: v_and_b32_e32 v4, 3, v5
1892+
; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 2
1893+
; GFX6-NEXT: v_ashrrev_i32_e32 v1, v4, v1
1894+
; GFX6-NEXT: v_and_b32_e32 v4, 3, v6
1895+
; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 2
1896+
; GFX6-NEXT: v_ashrrev_i32_e32 v2, v4, v2
1897+
; GFX6-NEXT: v_and_b32_e32 v4, 3, v7
1898+
; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 2
1899+
; GFX6-NEXT: v_ashrrev_i32_e32 v3, v4, v3
1900+
; GFX6-NEXT: s_setpc_b64 s[30:31]
1901+
;
1902+
; GFX8-LABEL: v_ashr_v4i2:
1903+
; GFX8: ; %bb.0:
1904+
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1905+
; GFX8-NEXT: v_and_b32_e32 v4, 3, v4
1906+
; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 2
1907+
; GFX8-NEXT: v_ashrrev_i16_e32 v0, v4, v0
1908+
; GFX8-NEXT: v_and_b32_e32 v4, 3, v5
1909+
; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 2
1910+
; GFX8-NEXT: v_ashrrev_i16_e32 v1, v4, v1
1911+
; GFX8-NEXT: v_and_b32_e32 v4, 3, v6
1912+
; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 2
1913+
; GFX8-NEXT: v_ashrrev_i16_e32 v2, v4, v2
1914+
; GFX8-NEXT: v_and_b32_e32 v4, 3, v7
1915+
; GFX8-NEXT: v_bfe_i32 v3, v3, 0, 2
1916+
; GFX8-NEXT: v_ashrrev_i16_e32 v3, v4, v3
1917+
; GFX8-NEXT: s_setpc_b64 s[30:31]
1918+
;
1919+
; GFX9-LABEL: v_ashr_v4i2:
1920+
; GFX9: ; %bb.0:
1921+
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1922+
; GFX9-NEXT: v_and_b32_e32 v4, 3, v4
1923+
; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 2
1924+
; GFX9-NEXT: v_ashrrev_i16_e32 v0, v4, v0
1925+
; GFX9-NEXT: v_and_b32_e32 v4, 3, v5
1926+
; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 2
1927+
; GFX9-NEXT: v_ashrrev_i16_e32 v1, v4, v1
1928+
; GFX9-NEXT: v_and_b32_e32 v4, 3, v6
1929+
; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 2
1930+
; GFX9-NEXT: v_ashrrev_i16_e32 v2, v4, v2
1931+
; GFX9-NEXT: v_and_b32_e32 v4, 3, v7
1932+
; GFX9-NEXT: v_bfe_i32 v3, v3, 0, 2
1933+
; GFX9-NEXT: v_ashrrev_i16_e32 v3, v4, v3
1934+
; GFX9-NEXT: s_setpc_b64 s[30:31]
1935+
;
1936+
; GFX10PLUS-LABEL: v_ashr_v4i2:
1937+
; GFX10PLUS: ; %bb.0:
1938+
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1939+
; GFX10PLUS-NEXT: v_and_b32_e32 v4, 3, v4
1940+
; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 2
1941+
; GFX10PLUS-NEXT: v_and_b32_e32 v5, 3, v5
1942+
; GFX10PLUS-NEXT: v_bfe_i32 v1, v1, 0, 2
1943+
; GFX10PLUS-NEXT: v_and_b32_e32 v6, 3, v6
1944+
; GFX10PLUS-NEXT: v_bfe_i32 v2, v2, 0, 2
1945+
; GFX10PLUS-NEXT: v_and_b32_e32 v7, 3, v7
1946+
; GFX10PLUS-NEXT: v_bfe_i32 v3, v3, 0, 2
1947+
; GFX10PLUS-NEXT: v_ashrrev_i16 v0, v4, v0
1948+
; GFX10PLUS-NEXT: v_ashrrev_i16 v1, v5, v1
1949+
; GFX10PLUS-NEXT: v_ashrrev_i16 v2, v6, v2
1950+
; GFX10PLUS-NEXT: v_ashrrev_i16 v3, v7, v3
1951+
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
1952+
%result = ashr <4 x i2> %value, %amount
1953+
ret <4 x i2> %result
1954+
}
1955+
1956+
; arithmetic shifts of an i1 are identity operations
1957+
define amdgpu_ps <4 x i1> @s_ashr_v4i1(<4 x i1> inreg %value, <4 x i1> inreg %amount) {
1958+
; GCN-LABEL: s_ashr_v4i1:
1959+
; GCN: ; %bb.0:
1960+
; GCN-NEXT: ; return to shader part epilog
1961+
;
1962+
; GFX10PLUS-LABEL: s_ashr_v4i1:
1963+
; GFX10PLUS: ; %bb.0:
1964+
; GFX10PLUS-NEXT: ; return to shader part epilog
1965+
%result = ashr <4 x i1> %value, %amount
1966+
ret <4 x i1> %result
1967+
}
1968+
1969+
define <4 x i1> @v_ashr_v4i1(<4 x i1> %value, <4 x i1> %amount) {
1970+
; GCN-LABEL: v_ashr_v4i1:
1971+
; GCN: ; %bb.0:
1972+
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1973+
; GCN-NEXT: s_setpc_b64 s[30:31]
1974+
;
1975+
; GFX10PLUS-LABEL: v_ashr_v4i1:
1976+
; GFX10PLUS: ; %bb.0:
1977+
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1978+
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
1979+
%result = ashr <4 x i1> %value, %amount
1980+
ret <4 x i1> %result
1981+
}
1982+
1983+
define amdgpu_ps <4 x i2> @s_ashr_v4i2(<4 x i2> inreg %value, <4 x i2> inreg %amount) {
1984+
; GCN-LABEL: s_ashr_v4i2:
1985+
; GCN: ; %bb.0:
1986+
; GCN-NEXT: s_and_b32 s4, s4, 3
1987+
; GCN-NEXT: s_bfe_i32 s0, s0, 0x20000
1988+
; GCN-NEXT: s_ashr_i32 s0, s0, s4
1989+
; GCN-NEXT: s_and_b32 s4, s5, 3
1990+
; GCN-NEXT: s_bfe_i32 s1, s1, 0x20000
1991+
; GCN-NEXT: s_ashr_i32 s1, s1, s4
1992+
; GCN-NEXT: s_and_b32 s4, s6, 3
1993+
; GCN-NEXT: s_bfe_i32 s2, s2, 0x20000
1994+
; GCN-NEXT: s_ashr_i32 s2, s2, s4
1995+
; GCN-NEXT: s_and_b32 s4, s7, 3
1996+
; GCN-NEXT: s_bfe_i32 s3, s3, 0x20000
1997+
; GCN-NEXT: s_ashr_i32 s3, s3, s4
1998+
; GCN-NEXT: ; return to shader part epilog
1999+
;
2000+
; GFX10PLUS-LABEL: s_ashr_v4i2:
2001+
; GFX10PLUS: ; %bb.0:
2002+
; GFX10PLUS-NEXT: s_and_b32 s4, s4, 3
2003+
; GFX10PLUS-NEXT: s_bfe_i32 s0, s0, 0x20000
2004+
; GFX10PLUS-NEXT: s_and_b32 s5, s5, 3
2005+
; GFX10PLUS-NEXT: s_bfe_i32 s1, s1, 0x20000
2006+
; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s4
2007+
; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, s5
2008+
; GFX10PLUS-NEXT: s_and_b32 s4, s6, 3
2009+
; GFX10PLUS-NEXT: s_bfe_i32 s2, s2, 0x20000
2010+
; GFX10PLUS-NEXT: s_and_b32 s5, s7, 3
2011+
; GFX10PLUS-NEXT: s_bfe_i32 s3, s3, 0x20000
2012+
; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, s4
2013+
; GFX10PLUS-NEXT: s_ashr_i32 s3, s3, s5
2014+
; GFX10PLUS-NEXT: ; return to shader part epilog
2015+
%result = ashr <4 x i2> %value, %amount
2016+
ret <4 x i2> %result
2017+
}
2018+
18842019
; FIXME: Argument lowering asserts
18852020
; define <2 x i65> @v_ashr_v2i65(<2 x i65> %value, <2 x i65> %amount) {
18862021
; %result = ashr <2 x i65> %value, %amount

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir‎

Lines changed: 0 additions & 174 deletions
Original file line numberDiff line numberDiff line change
@@ -969,176 +969,6 @@ body: |
969969
970970
...
971971

972-
---
973-
name: test_ashr_v4s1_v4s1
974-
body: |
975-
bb.0:
976-
liveins: $vgpr0, $vgpr1
977-
978-
; SI-LABEL: name: test_ashr_v4s1_v4s1
979-
; SI: liveins: $vgpr0, $vgpr1
980-
; SI-NEXT: {{ $}}
981-
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
982-
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
983-
; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
984-
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
985-
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
986-
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
987-
; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
988-
; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
989-
; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
990-
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
991-
; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
992-
; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
993-
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
994-
; SI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
995-
; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
996-
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C]]
997-
; SI-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 1
998-
; SI-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[AND1]](s32)
999-
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C]]
1000-
; SI-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 1
1001-
; SI-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG2]], [[AND2]](s32)
1002-
; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C]]
1003-
; SI-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 1
1004-
; SI-NEXT: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[AND3]](s32)
1005-
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
1006-
; SI-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
1007-
; SI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
1008-
; SI-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
1009-
; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C]]
1010-
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY2]](s32)
1011-
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
1012-
; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC1]]
1013-
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
1014-
; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ASHR2]], [[C]]
1015-
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[COPY3]](s32)
1016-
; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
1017-
; SI-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[OR]], [[TRUNC2]]
1018-
; SI-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
1019-
; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ASHR3]], [[C]]
1020-
; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY4]](s32)
1021-
; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
1022-
; SI-NEXT: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[TRUNC3]]
1023-
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR2]](s16)
1024-
; SI-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
1025-
; SI-NEXT: $vgpr0 = COPY [[AND8]](s32)
1026-
;
1027-
; VI-LABEL: name: test_ashr_v4s1_v4s1
1028-
; VI: liveins: $vgpr0, $vgpr1
1029-
; VI-NEXT: {{ $}}
1030-
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
1031-
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
1032-
; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
1033-
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
1034-
; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
1035-
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
1036-
; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
1037-
; VI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
1038-
; VI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
1039-
; VI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
1040-
; VI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
1041-
; VI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
1042-
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
1043-
; VI-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
1044-
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
1045-
; VI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
1046-
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
1047-
; VI-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC1]], [[AND]](s16)
1048-
; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
1049-
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
1050-
; VI-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 1
1051-
; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG1]](s32)
1052-
; VI-NEXT: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC3]], [[AND1]](s16)
1053-
; VI-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](s32)
1054-
; VI-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C4]]
1055-
; VI-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 1
1056-
; VI-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG2]](s32)
1057-
; VI-NEXT: [[ASHR2:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC5]], [[AND2]](s16)
1058-
; VI-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR5]](s32)
1059-
; VI-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C4]]
1060-
; VI-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 1
1061-
; VI-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG3]](s32)
1062-
; VI-NEXT: [[ASHR3:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC7]], [[AND3]](s16)
1063-
; VI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[ASHR]], [[C4]]
1064-
; VI-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[ASHR1]], [[C4]]
1065-
; VI-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C4]](s16)
1066-
; VI-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL]]
1067-
; VI-NEXT: [[AND6:%[0-9]+]]:_(s16) = G_AND [[ASHR2]], [[C4]]
1068-
; VI-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
1069-
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND6]], [[C5]](s16)
1070-
; VI-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[OR]], [[SHL1]]
1071-
; VI-NEXT: [[AND7:%[0-9]+]]:_(s16) = G_AND [[ASHR3]], [[C4]]
1072-
; VI-NEXT: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 3
1073-
; VI-NEXT: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND7]], [[C6]](s16)
1074-
; VI-NEXT: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[SHL2]]
1075-
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR2]](s16)
1076-
; VI-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
1077-
; VI-NEXT: $vgpr0 = COPY [[AND8]](s32)
1078-
;
1079-
; GFX9PLUS-LABEL: name: test_ashr_v4s1_v4s1
1080-
; GFX9PLUS: liveins: $vgpr0, $vgpr1
1081-
; GFX9PLUS-NEXT: {{ $}}
1082-
; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
1083-
; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
1084-
; GFX9PLUS-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
1085-
; GFX9PLUS-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
1086-
; GFX9PLUS-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
1087-
; GFX9PLUS-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
1088-
; GFX9PLUS-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
1089-
; GFX9PLUS-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
1090-
; GFX9PLUS-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
1091-
; GFX9PLUS-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
1092-
; GFX9PLUS-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
1093-
; GFX9PLUS-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
1094-
; GFX9PLUS-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
1095-
; GFX9PLUS-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
1096-
; GFX9PLUS-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
1097-
; GFX9PLUS-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
1098-
; GFX9PLUS-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
1099-
; GFX9PLUS-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC1]], [[AND]](s16)
1100-
; GFX9PLUS-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
1101-
; GFX9PLUS-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
1102-
; GFX9PLUS-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 1
1103-
; GFX9PLUS-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG1]](s32)
1104-
; GFX9PLUS-NEXT: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC3]], [[AND1]](s16)
1105-
; GFX9PLUS-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](s32)
1106-
; GFX9PLUS-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C4]]
1107-
; GFX9PLUS-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 1
1108-
; GFX9PLUS-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG2]](s32)
1109-
; GFX9PLUS-NEXT: [[ASHR2:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC5]], [[AND2]](s16)
1110-
; GFX9PLUS-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR5]](s32)
1111-
; GFX9PLUS-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C4]]
1112-
; GFX9PLUS-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 1
1113-
; GFX9PLUS-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG3]](s32)
1114-
; GFX9PLUS-NEXT: [[ASHR3:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC7]], [[AND3]](s16)
1115-
; GFX9PLUS-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[ASHR]], [[C4]]
1116-
; GFX9PLUS-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[ASHR1]], [[C4]]
1117-
; GFX9PLUS-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C4]](s16)
1118-
; GFX9PLUS-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL]]
1119-
; GFX9PLUS-NEXT: [[AND6:%[0-9]+]]:_(s16) = G_AND [[ASHR2]], [[C4]]
1120-
; GFX9PLUS-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
1121-
; GFX9PLUS-NEXT: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND6]], [[C5]](s16)
1122-
; GFX9PLUS-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[OR]], [[SHL1]]
1123-
; GFX9PLUS-NEXT: [[AND7:%[0-9]+]]:_(s16) = G_AND [[ASHR3]], [[C4]]
1124-
; GFX9PLUS-NEXT: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 3
1125-
; GFX9PLUS-NEXT: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND7]], [[C6]](s16)
1126-
; GFX9PLUS-NEXT: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[SHL2]]
1127-
; GFX9PLUS-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR2]](s16)
1128-
; GFX9PLUS-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
1129-
; GFX9PLUS-NEXT: $vgpr0 = COPY [[AND8]](s32)
1130-
%0:_(s32) = COPY $vgpr0
1131-
%1:_(s32) = COPY $vgpr1
1132-
%2:_(s4) = G_TRUNC %0
1133-
%3:_(s4) = G_TRUNC %1
1134-
%4:_(<4 x s1>) = G_BITCAST %2
1135-
%5:_(<4 x s1>) = G_BITCAST %3
1136-
%6:_(<4 x s1>) = G_ASHR %4, %5
1137-
%7:_(s4) = G_BITCAST %6
1138-
%8:_(s32) = G_ZEXT %7
1139-
$vgpr0 = COPY %8
1140-
...
1141-
1142972
---
1143973
name: test_ashr_v4s16_v4s16
1144974
body: |
@@ -2428,7 +2258,3 @@ body: |
24282258
%6:_(s96) = G_ANYEXT %5
24292259
$vgpr0_vgpr1_vgpr2 = COPY %6
24302260
...
2431-
## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
2432-
# GFX9PLUS: {{.*}}
2433-
# SI: {{.*}}
2434-
# VI: {{.*}}

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