fixup! shamt

Author: 4vtomat

llvm/lib/Target/RISCV/RISCVInstrInfoP.td

@@ -21,6 +21,7 @@
 def simm10 : RISCVSImmOp<10>, TImmLeaf<XLenVT, "return isInt<10>(Imm);">;
 def tuimm3 : RISCVUImmOp<3>, TImmLeaf<XLenVT, "return isUInt<3>(Imm);">;
 def tuimm4 : RISCVUImmOp<4>, TImmLeaf<XLenVT, "return isUInt<4>(Imm);">;
+def tuimm5 : RISCVUImmOp<5>, TImmLeaf<XLenVT, "return isUInt<5>(Imm);">;
 
 def SImm8UnsignedAsmOperand : SImmAsmOperand<8, "Unsigned"> {
   let RenderMethod = "addSImm8UnsignedOperands";
@@ -1557,8 +1558,8 @@ let Predicates = [HasStdExtP, IsRV64] in {
   def: Pat<(v2i32 (riscv_pasubu GPR:$rs1, GPR:$rs2)), (PASUBU_W GPR:$rs1, GPR:$rs2)>;
 
   // 32-bit logical shift left patterns
-  def: Pat<(v2i32 (shl GPR:$rs1, (v2i32 (riscv_pli tuimm4:$shamt)))),
-           (PSLLI_W GPR:$rs1, tuimm4:$shamt)>;
+  def: Pat<(v2i32 (shl GPR:$rs1, (v2i32 (riscv_pli tuimm5:$shamt)))),
+           (PSLLI_W GPR:$rs1, tuimm5:$shamt)>;
 
   // 32-bit signed saturation shift left patterns
   def: Pat<(v2i32 (sshlsat GPR:$rs1, (v2i32 (riscv_pli tuimm4:$shamt)))),