[AArch64] Refactor move_vec_shift operand def and update operand type handling and testcase

Author: lakshayk-nv

llvm/lib/Target/AArch64/AArch64InstrFormats.td

@@ -1238,17 +1238,6 @@ def timm32_0_255 : Operand<i32>, TImmLeaf<i32, [{
 
 } // let OperandType = "OPERAND_IMMEDIATE"
 
-let OperandType = "OPERAND_MSL_SHIFT" in {
-  // A vector move shifter operand:
-  //  {0} - imm1: #8 or #16
-  def move_vec_shift : Operand<i32> {
-    let PrintMethod = "printShifter";
-    let OperandNamespace = "AArch64";
-    let EncoderMethod = "getMoveVecShifterOpValue";
-    let ParserMatchClass = MoveVecShifterOperand;
-  }
-} // let OperandType = "OPERAND_MSL_SHIFT"
-
 // An arithmetic shifter operand:
 //  {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr
 //  {5-0} - imm6
@@ -1327,6 +1316,16 @@ def logical_vec_hw_shift : Operand<i32> {
   let ParserMatchClass = LogicalVecHalfWordShifterOperand;
 }
 
+// A vector move shifter operand:
+//  {0} - imm1: #8 or #16
+def move_vec_shift : Operand<i32> {
+  let PrintMethod = "printShifter";
+  let EncoderMethod = "getMoveVecShifterOpValue";
+  let ParserMatchClass = MoveVecShifterOperand;
+  let OperandType = "OPERAND_SHIFT_MSL";
+  let OperandNamespace = "AArch64";
+}
+
 let DiagnosticType = "AddSubSecondSource" in {
   def AddSubImmOperand : AsmOperandClass {
     let Name = "AddSubImm";

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h

@@ -70,7 +70,7 @@ bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII);
 namespace AArch64 {
 enum OperandType {
   OPERAND_IMPLICIT_IMM_0 = MCOI::OPERAND_FIRST_TARGET,
-  OPERAND_MSL_SHIFT
+  OPERAND_SHIFT_MSL,
 };
 } // namespace AArch64
 

llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s

@@ -2,29 +2,6 @@
 
 
 
-// Test for omitting OperandType::OPERAND_UNKNOWN
-
-// ADDXri: ADD Xd, Xn, #imm{, shift}
-# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=ADDXri 2>&1 | FileCheck %s --check-prefix=ADDXri_latency
-# ADDXri_latency-NOT: Not all operands were initialized by the snippet generator for ADDXri opcode
-# ADDXri_latency:      ---
-# ADDXri_latency-NEXT: mode: latency
-# ADDXri_latency-NEXT: key:
-# ADDXri_latency-NEXT:   instructions:
-# ADDXri_latency-NEXT:     ADDXri [[REG1:X[0-9]+|LR]] [[REG2:X[0-9]+|LR]] i_0x0 i_0x0
-# ADDXri_latency: ...
-
-# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=ADDXri 2>&1 | FileCheck %s --check-prefix=ADDXri_throughput
-# ADDXri_throughput-NOT: Not all operands were initialized by the snippet generator for ADDXri opcode
-# ADDXri_throughput:      ---
-# ADDXri_throughput-NEXT: mode: inverse_throughput
-# ADDXri_throughput-NEXT: key:
-# ADDXri_throughput-NEXT:   instructions:
-# ADDXri_throughput-NEXT:     ADDXri [[REG1:X[0-9]+|LR]] [[REG2:X[0-9]+|LR]] i_0x0 i_0x0
-# ADDXri_throughput: ...
-
-
-
 // Test for omitting OperandType::OPERAND_MSL_SHIFT_4S
 
 // MOVIv2s_msl: MOVI vd, #imm{, shift}

llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp

@@ -173,13 +173,9 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand(
   //   encodings or unreliable benchmark results for these system-level
   //   instructions.
   switch (OperandType) {
-  case MCOI::OperandType::OPERAND_UNKNOWN: {
-    AssignedValue = MCOperand::createImm(0);
-    return Error::success();
-  }
   // MSL (Masking Shift Left) imm operand for 32-bit splatted SIMD constants
   // Correspond to AArch64InstructionSelector::tryAdvSIMDModImm321s()
-  case llvm::AArch64::OPERAND_MSL_SHIFT: {
+  case llvm::AArch64::OPERAND_SHIFT_MSL: {
     // There are two valid encodings:
     //   - Type 7: imm at [15:8], [47:40], shift = 264 (0x108) → msl #8
     //   - Type 8: imm at [23:16], [55:48], shift = 272 (0x110) → msl #16
@@ -189,8 +185,8 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand(
     AssignedValue = MCOperand::createImm(264);
     return Error::success();
   }
+  case llvm::AArch64::OPERAND_IMPLICIT_IMM_0:
   case MCOI::OperandType::OPERAND_PCREL:
-  case MCOI::OperandType::OPERAND_FIRST_TARGET:
     AssignedValue = MCOperand::createImm(0);
     return Error::success();
   default:

llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp

@@ -276,9 +276,7 @@ static Error randomizeMCOperand(const LLVMState &State,
     AssignedValue = MCOperand::createReg(randomBit(AllowedRegs));
     break;
   }
-  /// Omit unknown and pc-relative operands to imm value based on the
-  /// instruction
-  case MCOI::OperandType::OPERAND_UNKNOWN:
+  /// Omit pc-relative operands to imm value based on the instruction
   case MCOI::OperandType::OPERAND_PCREL:
     return State.getExegesisTarget().randomizeTargetMCOperand(
         Instr, Var, AssignedValue, ForbiddenRegs);