[RISCV] Add xsmtvdot extension support for SPACEMIT_X60 target.

Author: link-xyq

clang/test/Driver/riscv-cpus.c

@@ -41,38 +41,38 @@
 // MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+b"
 // MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+v"
 // MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+h"
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zic64b" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicbom" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicbop" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicboz" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccamoa" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccif" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicclsm" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccrse" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicntr" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicond" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicsr" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zihintntl" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zacas" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zawrs" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zfa" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zfh" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zca" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zcb" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zcmop" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zba" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbb" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zic64b"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicbom"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicbop"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicboz"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccamoa"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccif"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicclsm"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccrse"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicntr"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicond"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicsr"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zihintntl"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zacas"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zawrs"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zfa"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zfh"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zca"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zcb"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zcmop"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zba"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbb"
 // MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbc"
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkb" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkc" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkx" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkb"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkc"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkx"
 // MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbs"
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zkn" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zks" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvbb" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64d" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64f" 
-// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64x" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zkn"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zks"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvbb"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64d"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64f"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64x"
 // MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvfh"
 // MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvkb"
 // MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvkt"
@@ -157,6 +157,7 @@
 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svinval"
 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svnapot"
 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svpbmt"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+xsmtvdot"
 // MCPU-SPACEMIT-X60-SAME: "-target-abi" "lp64d"
 
 // We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string.

llvm/lib/Target/RISCV/RISCVProcessors.td

@@ -673,6 +673,7 @@ def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
                                         FeatureStdExtZvfh,
                                         FeatureStdExtZvkt,
                                         FeatureStdExtZvl256b,
+                                        FeatureVendorXSMTVDot,
                                         FeatureUnalignedScalarMem]),
                                        [TuneDLenFactor2,
                                         TuneOptimizedNF2SegmentLoadStore,