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[AMDGPU]
1 parent ec3de57 commit 967bce6

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3 files changed

+58
-25
lines changed

3 files changed

+58
-25
lines changed

llvm/include/llvm/CodeGen/TargetSubtargetInfo.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
#include "llvm/ADT/ArrayRef.h"
1717
#include "llvm/ADT/SmallVector.h"
1818
#include "llvm/ADT/StringRef.h"
19+
#include "llvm/CodeGen/MachineBasicBlock.h"
1920
#include "llvm/CodeGen/MacroFusion.h"
2021
#include "llvm/CodeGen/PBQPRAConstraint.h"
2122
#include "llvm/CodeGen/SchedulerRegistry.h"

llvm/lib/Target/AMDGPU/GCNSubtarget.cpp

Lines changed: 55 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,11 @@ static cl::opt<unsigned>
5252
cl::desc("Number of addresses from which to enable MIMG NSA."),
5353
cl::init(2), cl::Hidden);
5454

55+
static cl::opt<std::string>
56+
AMDGPUPostRADirection("amdgpu-post-ra-direction",
57+
cl::desc("Select custom AMDGPU postRA direction."),
58+
cl::Hidden, cl::init(""));
59+
5560
GCNSubtarget::~GCNSubtarget() = default;
5661

5762
GCNSubtarget &GCNSubtarget::initializeSubtargetDependencies(const Triple &TT,
@@ -341,37 +346,63 @@ void GCNSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
341346
}
342347

343348
void GCNSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy,
344-
unsigned NumRegionInstrs) const {
345-
switch (getPostRASchedDirection()) {
346-
case MISched::TopDown:
349+
const MachineBasicBlock &MBB,
350+
unsigned NumRegionInstr) const {
351+
const Function &F = MBB.getParent()->getFunction();
352+
Attribute PostRADirectionAttr = F.getFnAttribute("amdgpu-post-ra-direction");
353+
if (!PostRADirectionAttr.isValid())
354+
return;
355+
356+
StringRef PostRADirectionStr = PostRADirectionAttr.getValueAsString();
357+
if (PostRADirectionStr == "topdown") {
347358
Policy.OnlyTopDown = true;
348359
Policy.OnlyBottomUp = false;
349-
break;
350-
case MISched::BottomUp:
360+
} else if (PostRADirectionStr == "bottomup") {
351361
Policy.OnlyTopDown = false;
352362
Policy.OnlyBottomUp = true;
353-
break;
354-
case MISched::Bidirectional:
355-
default:
363+
} else if (PostRADirectionStr == "bidirectional") {
356364
Policy.OnlyTopDown = false;
357365
Policy.OnlyBottomUp = false;
358-
break;
366+
} else {
367+
DiagnosticInfoOptimizationFailure Diag(
368+
F, F.getSubprogram(),
369+
Twine("invalid value for postRa direction attribute: '") +
370+
PostRADirectionStr);
371+
F.getContext().diagnose(Diag);
359372
}
360-
361-
LLVM_DEBUG({
362-
const char *DirStr = "topdown";
363-
switch (getPostRASchedDirection()) {
364-
case MISched::BottomUp:
365-
DirStr = "bottomup";
366-
break;
367-
case MISched::Bidirectional:
368-
DirStr = "bidirectional";
369-
break;
370-
default:
371-
break;
372-
}
373-
dbgs() << "Post-MI-sched direction: " << DirStr << '\n';
374-
});
373+
// }
374+
375+
// switch (getPostRASchedDirection()) {
376+
// case MISched::TopDown:
377+
// Policy.OnlyTopDown = true;
378+
// Policy.OnlyBottomUp = false;
379+
// break;
380+
// case MISched::BottomUp:
381+
// Policy.OnlyTopDown = false;
382+
// Policy.OnlyBottomUp = true;
383+
// break;
384+
// case MISched::Bidirectional:
385+
// Policy.OnlyTopDown = false;
386+
// Policy.OnlyBottomUp = false;
387+
// break;
388+
// default:
389+
// break;
390+
// }
391+
392+
// LLVM_DEBUG({
393+
// const char *DirStr = "topdown";
394+
// switch (getPostRASchedDirection()) {
395+
// case MISched::BottomUp:
396+
// DirStr = "bottomup";
397+
// break;
398+
// case MISched::Bidirectional:
399+
// DirStr = "bidirectional";
400+
// break;
401+
// default:
402+
// break;
403+
// }
404+
// dbgs() << "Post-MI-sched direction: " << DirStr << '\n';
405+
// });
375406
}
376407

377408
void GCNSubtarget::mirFileLoaded(MachineFunction &MF) const {

llvm/lib/Target/AMDGPU/GCNSubtarget.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1042,7 +1042,8 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
10421042
const SchedRegion &Region) const override;
10431043

10441044
void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
1045-
unsigned NumRegionInstrs) const override;
1045+
const MachineBasicBlock &MBB,
1046+
unsigned NumRegionInstr) const override;
10461047

10471048
void mirFileLoaded(MachineFunction &MF) const override;
10481049

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