[[lvm-exegesis] [AArch64] Updated PCREL imm value to 8 and Updated comments.

Author: lakshayk-nv

llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s

@@ -2,7 +2,7 @@
 
 
 
-// Test for omitting OperandType::OPERAND_MSL_SHIFT_4S
+// Test for omitting OperandType::OPERAND_SHIFT_MSL
 
 // MOVIv2s_msl: MOVI vd, #imm{, shift}
 # RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency  --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv4s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv4s_msl_latency
@@ -20,10 +20,6 @@
 # MOVIv4s_msl_throughput-NEXT:     MOVIv4s_msl [[REG1:Q[0-9]+|LR]] i_0x1 i_0x108
 # MOVIv4s_msl_throughput: ...
 
-
-
-// Test for omitting OperandType::OPERAND_MSL_SHIFT_2S
-
 // MOVIv2s_msl: MOVI vd, #imm{, shift}
 # RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency  --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv2s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv2s_msl_latency
 # RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv2s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv2s_msl_throughput
@@ -54,12 +50,12 @@
 # LDRDl_throughput-NEXT: mode: inverse_throughput
 # LDRDl_throughput-NEXT: key:
 # LDRDl_throughput-NEXT:   instructions:
-# LDRDl_throughput-NEXT:     LDRDl [[REG1:D[0-9]+|LR]] i_0x0
+# LDRDl_throughput-NEXT:     LDRDl [[REG1:D[0-9]+|LR]] i_0x8
 # LDRDl_throughput: ...
 
 
 
-// Test for omitting OperandType::OPERAND_FIRST_TARGET
+// Test for omitting OperandType::OPERAND_IMPLICIT_IMM_0
 
 // UMOVvi16_idx0: UMOV wd, vn.h[index]
 # RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=UMOVvi16_idx0 2>&1 | FileCheck %s --check-prefix=UMOVvi16_idx0_latency

llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp

@@ -161,17 +161,23 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand(
     const BitVector &ForbiddenRegs) const {
   const Operand &Op = Instr.getPrimaryOperand(Var);
   const auto OperandType = Op.getExplicitOperandInfo().OperandType;
-  //  FIXME: Implement opcode-specific immediate value handling for system
-  //  instructions:
+  // NOTE: To resolve "Not all operands were initialized by snippet generator"
+  // Requires OperandType to be defined for such opcode's operands in AArch64
+  // tablegen files. And omit introduced OperandType(s).
+
+  // Hacky temporary fix works by defaulting all OPERAND_UNKNOWN to
+  // immediate value 0, but this introduce illegal instruction error for below
+  // system instructions will need to be omitted with OperandType or opcode
+  // specific values to avoid generating invalid encodings or unreliable
+  // benchmark results for these system-level instructions.
+  //  Implement opcode-specific immediate value handling for system instrs:
   //   - MRS/MSR: Use valid system register encodings (e.g., NZCV, FPCR, FPSR)
   //   - MSRpstatesvcrImm1: Use valid PSTATE field encodings (e.g., SPSel,
   //   DAIFSet)
   //   - SYSLxt/SYSxt: Use valid system instruction encodings with proper
   //   CRn/CRm/op values
   //   - UDF: Use valid undefined instruction immediate ranges (0-65535)
-  //   Currently defaulting to immediate value 0, which may cause invalid
-  //   encodings or unreliable benchmark results for these system-level
-  //   instructions.
+
   switch (OperandType) {
   // MSL (Masking Shift Left) imm operand for 32-bit splatted SIMD constants
   // Correspond to AArch64InstructionSelector::tryAdvSIMDModImm321s()
@@ -186,9 +192,11 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand(
     return Error::success();
   }
   case llvm::AArch64::OPERAND_IMPLICIT_IMM_0:
-  case MCOI::OperandType::OPERAND_PCREL:
     AssignedValue = MCOperand::createImm(0);
     return Error::success();
+  case MCOI::OperandType::OPERAND_PCREL:
+    AssignedValue = MCOperand::createImm(8);
+    return Error::success();
   default:
     break;
   }