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WIP: Add addlike PatFrags for AVX-512 instruction folding
- Define addlike PatFrags to match both ADD and disjoint OR - Update avx512_binop_rm multiclass chain to use SDPatternOperator - Apply addlike to VPADD instructions Status: 34 test failures - need guidance on pattern scope
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2 files changed

+21
-14
lines changed

2 files changed

+21
-14
lines changed

‎llvm/include/llvm/Target/TargetSelectionDAG.td‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1177,6 +1177,13 @@ def or_disjoint : PatFrag<(ops node:$lhs, node:$rhs),
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}];
11781178
}
11791179

1180+
def addlike : PatFrags<(ops node:$lhs, node:$rhs),
1181+
[(add node:$lhs, node:$rhs), (or node:$lhs, node:$rhs)],[{
1182+
if (Op.getOpcode() == ISD::ADD)
1183+
return true;
1184+
return CurDAG->isADDLike(Op);
1185+
}]>;
1186+
11801187
def xor_like : PatFrags<(ops node:$lhs, node:$rhs),
11811188
[(xor node:$lhs, node:$rhs),
11821189
(or_disjoint node:$lhs, node:$rhs)]>;

‎llvm/lib/Target/X86/X86InstrAVX512.td‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -4685,7 +4685,7 @@ let Predicates = [HasVLX], AddedComplexity = 400 in {
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//===----------------------------------------------------------------------===//
46864686
// AVX-512 - Integer arithmetic
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//
4688-
multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4688+
multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
46894689
X86VectorVTInfo _, X86FoldableSchedWrite sched,
46904690
bit IsCommutable = 0> {
46914691
defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
@@ -4704,7 +4704,7 @@ multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
47044704
Sched<[sched.Folded, sched.ReadAfterFold]>;
47054705
}
47064706

4707-
multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
4707+
multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
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X86VectorVTInfo _, X86FoldableSchedWrite sched,
47094709
bit IsCommutable = 0> :
47104710
avx512_binop_rm<opc, OpcodeStr, OpNode, _, sched, IsCommutable> {
@@ -4719,7 +4719,7 @@ multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
47194719
Sched<[sched.Folded, sched.ReadAfterFold]>;
47204720
}
47214721

4722-
multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
4722+
multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
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AVX512VLVectorVTInfo VTInfo,
47244724
X86SchedWriteWidths sched, Predicate prd,
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bit IsCommutable = 0> {
@@ -4735,7 +4735,7 @@ multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
47354735
}
47364736
}
47374737

4738-
multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
4738+
multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
47394739
AVX512VLVectorVTInfo VTInfo,
47404740
X86SchedWriteWidths sched, Predicate prd,
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bit IsCommutable = 0> {
@@ -4751,30 +4751,30 @@ multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
47514751
}
47524752
}
47534753

4754-
multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
4754+
multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
47554755
X86SchedWriteWidths sched, Predicate prd,
47564756
bit IsCommutable = 0> {
47574757
defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
47584758
sched, prd, IsCommutable>,
47594759
REX_W, EVEX_CD8<64, CD8VF>;
47604760
}
47614761

4762-
multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
4762+
multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
47634763
X86SchedWriteWidths sched, Predicate prd,
47644764
bit IsCommutable = 0> {
47654765
defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
47664766
sched, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
47674767
}
47684768

4769-
multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
4769+
multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
47704770
X86SchedWriteWidths sched, Predicate prd,
47714771
bit IsCommutable = 0> {
47724772
defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
47734773
sched, prd, IsCommutable>, EVEX_CD8<16, CD8VF>,
47744774
WIG;
47754775
}
47764776

4777-
multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
4777+
multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
47784778
X86SchedWriteWidths sched, Predicate prd,
47794779
bit IsCommutable = 0> {
47804780
defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
@@ -4783,7 +4783,7 @@ multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
47834783
}
47844784

47854785
multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
4786-
SDNode OpNode, X86SchedWriteWidths sched,
4786+
SDPatternOperator OpNode, X86SchedWriteWidths sched,
47874787
Predicate prd, bit IsCommutable = 0> {
47884788
defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr#"q", OpNode, sched, prd,
47894789
IsCommutable>;
@@ -4793,7 +4793,7 @@ multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
47934793
}
47944794

47954795
multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
4796-
SDNode OpNode, X86SchedWriteWidths sched,
4796+
SDPatternOperator OpNode, X86SchedWriteWidths sched,
47974797
Predicate prd, bit IsCommutable = 0> {
47984798
defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr#"w", OpNode, sched, prd,
47994799
IsCommutable>;
@@ -4804,7 +4804,7 @@ multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
48044804

48054805
multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
48064806
bits<8> opc_d, bits<8> opc_q,
4807-
string OpcodeStr, SDNode OpNode,
4807+
string OpcodeStr, SDPatternOperator OpNode,
48084808
X86SchedWriteWidths sched,
48094809
bit IsCommutable = 0> {
48104810
defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
@@ -4815,7 +4815,7 @@ multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
48154815

48164816
multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
48174817
X86FoldableSchedWrite sched,
4818-
SDNode OpNode,X86VectorVTInfo _Src,
4818+
SDPatternOperator OpNode,X86VectorVTInfo _Src,
48194819
X86VectorVTInfo _Dst, X86VectorVTInfo _Brdct,
48204820
bit IsCommutable = 0> {
48214821
defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
@@ -4847,7 +4847,7 @@ multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
48474847
}
48484848
}
48494849

4850-
defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
4850+
defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", addlike,
48514851
SchedWriteVecALU, 1>;
48524852
defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
48534853
SchedWriteVecALU, 0>;
@@ -4882,7 +4882,7 @@ multiclass avx512_binop_all<bits<8> opc, string OpcodeStr,
48824882
X86SchedWriteWidths sched,
48834883
AVX512VLVectorVTInfo _SrcVTInfo,
48844884
AVX512VLVectorVTInfo _DstVTInfo,
4885-
SDNode OpNode, list<Predicate> prds512,
4885+
SDPatternOperator OpNode, list<Predicate> prds512,
48864886
list<Predicate> prds,
48874887
X86VectorVTInfo _VTInfo512 = _SrcVTInfo.info512,
48884888
X86VectorVTInfo _VTInfo256 = _SrcVTInfo.info256,

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