@@ -704,39 +704,105 @@ def test_riscv64_regs_gpr_fpr(self):
704704 process = target .LoadCore ("linux-riscv64.gpr_fpr.core" )
705705
706706 values = {}
707+ alias = {}
707708 values ["pc" ] = "0x000000000001016e"
709+
708710 values ["ra" ] = "0x00000000000101a4"
711+ alias ["x1" ] = "ra"
712+
709713 values ["sp" ] = "0x0000003fffc1d2d0"
714+ alias ["x2" ] = "sp"
715+
710716 values ["gp" ] = "0x0000002ae6eccf50"
717+ alias ["x3" ] = "gp"
718+
711719 values ["tp" ] = "0x0000003ff3cb5400"
720+ alias ["x4" ] = "tp"
721+
712722 values ["t0" ] = "0x7f7f7f7fffffffff"
723+ alias ["x5" ] = "t0"
724+
713725 values ["t1" ] = "0x0000002ae6eb9b1c"
726+ alias ["x6" ] = "t1"
727+
714728 values ["t2" ] = "0xffffffffffffffff"
729+ alias ["x7" ] = "t2"
730+
715731 values ["fp" ] = "0x0000003fffc1d300"
732+ alias ["x8" ] = "fp"
733+
716734 values ["s1" ] = "0x0000002ae6eced98"
735+ alias ["x9" ] = "s1"
736+
717737 values ["a0" ] = "0x0"
738+ alias ["x10" ] = "a0"
739+
718740 values ["a1" ] = "0x0000000000010144"
741+ alias ["x11" ] = "a1"
742+
719743 values ["a2" ] = "0x0000002ae6ecedb0"
744+ alias ["x12" ] = "a2"
745+
720746 values ["a3" ] = "0xafdbdbff81cf7f81"
747+ alias ["x13" ] = "a3"
748+
721749 values ["a4" ] = "0x00000000000101e4"
750+ alias ["x14" ] = "a4"
751+
722752 values ["a5" ] = "0x0"
753+ alias ["x15" ] = "a5"
754+
723755 values ["a6" ] = "0x2f5b5a40014e0001"
756+ alias ["x16" ] = "a6"
757+
724758 values ["a7" ] = "0x00000000000000dd"
759+ alias ["x17" ] = "a7"
760+
725761 values ["s2" ] = "0x0000002ae6ec8860"
762+ alias ["x18" ] = "s2"
763+
726764 values ["s3" ] = "0x0000002ae6ecedb0"
765+ alias ["x19" ] = "s3"
766+
727767 values ["s4" ] = "0x0000003fff886c18"
768+ alias ["x20" ] = "s4"
769+
728770 values ["s5" ] = "0x0000002ae6eceb78"
771+ alias ["x21" ] = "s5"
772+
729773 values ["s6" ] = "0x0000002ae6ec8860"
774+ alias ["x22" ] = "s6"
775+
730776 values ["s7" ] = "0x0000002ae6ec8860"
777+ alias ["x23" ] = "s7"
778+
731779 values ["s8" ] = "0x0"
780+ alias ["x24" ] = "s8"
781+
732782 values ["s9" ] = "0x000000000000000f"
783+ alias ["x25" ] = "s9"
784+
733785 values ["s10" ] = "0x0000002ae6ecc8d0"
786+ alias ["x26" ] = "s10"
787+
734788 values ["s11" ] = "0x0000000000000008"
789+ alias ["x27" ] = "s11"
790+
735791 values ["t3" ] = "0x0000003ff3be3728"
792+ alias ["x28" ] = "t3"
793+
736794 values ["t4" ] = "0x0"
795+ alias ["x29" ] = "t4"
796+
737797 values ["t5" ] = "0x0000000000000002"
798+ alias ["x30" ] = "t5"
799+
738800 values ["t6" ] = "0x0000002ae6ed08b9"
801+ alias ["x31" ] = "t6"
802+
739803 values ["zero" ] = "0x0"
804+ alias ["x0" ] = "zero"
805+
740806 values ["fa5" ] = "0xffffffff423c0000"
741807 values ["fcsr" ] = "0x00000000"
742808
@@ -788,6 +854,13 @@ def test_riscv64_regs_gpr_fpr(self):
788854 substrs = ["{} = {}" .format (regname , fpr_value )],
789855 )
790856
857+ for aliasname , regname in alias .items ():
858+ value = values [regname ]
859+ self .expect (
860+ "register read {}" .format (aliasname ),
861+ substrs = ["{} = {}" .format (regname , value )],
862+ )
863+
791864 self .expect ("register read --all" )
792865
793866 @skipIfLLVMTargetMissing ("RISCV" )
@@ -798,46 +871,118 @@ def test_riscv64_regs_gpr_only(self):
798871 process = target .LoadCore ("linux-riscv64.gpr_only.core" )
799872
800873 values = {}
874+ alias = {}
801875 values ["pc" ] = "0x0000000000010164"
876+
802877 values ["ra" ] = "0x0000000000010194"
878+ alias ["x1" ] = "ra"
879+
803880 values ["sp" ] = "0x00fffffff4d5fcc0"
881+ alias ["x2" ] = "sp"
882+
804883 values ["gp" ] = "0x0000000000157678"
884+ alias ["x3" ] = "gp"
885+
805886 values ["tp" ] = "0x00ffffff99c43400"
887+ alias ["x4" ] = "tp"
888+
806889 values ["t0" ] = "0x00ffffff99c6b260"
890+ alias ["x5" ] = "t0"
891+
807892 values ["t1" ] = "0x00ffffff99b7bd54"
893+ alias ["x6" ] = "t1"
894+
808895 values ["t2" ] = "0x0000000003f0b27f"
896+ alias ["x7" ] = "t2"
897+
809898 values ["fp" ] = "0x00fffffff4d5fcf0"
899+ alias ["x8" ] = "fp"
900+
810901 values ["s1" ] = "0x0000000000000003"
902+ alias ["x9" ] = "s1"
903+
811904 values ["a0" ] = "0x0"
905+ alias ["x10" ] = "a0"
906+
812907 values ["a1" ] = "0x0000000000010144"
908+ alias ["x11" ] = "a1"
909+
813910 values ["a2" ] = "0x0000000000176460"
911+ alias ["x12" ] = "a2"
912+
814913 values ["a3" ] = "0x000000000015ee38"
914+ alias ["x13" ] = "a3"
915+
815916 values ["a4" ] = "0x00000000423c0000"
917+ alias ["x14" ] = "a4"
918+
816919 values ["a5" ] = "0x0"
920+ alias ["x15" ] = "a5"
921+
817922 values ["a6" ] = "0x0"
923+ alias ["x16" ] = "a6"
924+
818925 values ["a7" ] = "0x00000000000000dd"
926+ alias ["x17" ] = "a7"
927+
819928 values ["s2" ] = "0x0"
929+ alias ["x18" ] = "s2"
930+
820931 values ["s3" ] = "0x000000000014ddf8"
932+ alias ["x19" ] = "s3"
933+
821934 values ["s4" ] = "0x000000000003651c"
935+ alias ["x20" ] = "s4"
936+
822937 values ["s5" ] = "0x00fffffffccd8d28"
938+ alias ["x21" ] = "s5"
939+
823940 values ["s6" ] = "0x000000000014ddf8"
941+ alias ["x22" ] = "s6"
942+
824943 values ["s7" ] = "0x00ffffff99c69d48"
944+ alias ["x23" ] = "s7"
945+
825946 values ["s8" ] = "0x00ffffff99c6a008"
947+ alias ["x24" ] = "s8"
948+
826949 values ["s9" ] = "0x0"
950+ alias ["x25" ] = "s9"
951+
827952 values ["s10" ] = "0x0"
953+ alias ["x26" ] = "s10"
954+
828955 values ["s11" ] = "0x0"
956+ alias ["x27" ] = "s11"
957+
829958 values ["t3" ] = "0x00ffffff99c42000"
959+ alias ["x28" ] = "t3"
960+
830961 values ["t4" ] = "0x00ffffff99af8e20"
962+ alias ["x29" ] = "t4"
963+
831964 values ["t5" ] = "0x0000000000000005"
965+ alias ["x30" ] = "t5"
966+
832967 values ["t6" ] = "0x44760bdd8d5f6381"
968+ alias ["x31" ] = "t6"
969+
833970 values ["zero" ] = "0x0"
971+ alias ["x0" ] = "zero"
834972
835973 for regname , value in values .items ():
836974 self .expect (
837975 "register read {}" .format (regname ),
838976 substrs = ["{} = {}" .format (regname , value )],
839977 )
840978
979+ for aliasname , regname in alias .items ():
980+ value = values [regname ]
981+ self .expect (
982+ "register read {}" .format (aliasname ),
983+ substrs = ["{} = {}" .format (regname , value )],
984+ )
985+
841986 # Check that LLDB does not try to read other registers from core file
842987 self .expect (
843988 "register read --all" ,
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