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Rename StackID
Change-Id: I7962db144b15cf77e0f5a59ad39ee6ed097c1fc0
1 parent 2ae8d09 commit 9ee2f69

12 files changed

+36
-35
lines changed

‎llvm/include/llvm/CodeGen/MIRYamlMapping.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -378,7 +378,8 @@ struct ScalarEnumerationTraits<TargetStackID::Value> {
378378
IO.enumCase(ID, "default", TargetStackID::Default);
379379
IO.enumCase(ID, "sgpr-spill", TargetStackID::SGPRSpill);
380380
IO.enumCase(ID, "scalable-vector", TargetStackID::ScalableVector);
381-
IO.enumCase(ID, "scalable-pred-vector", TargetStackID::ScalablePredVector);
381+
IO.enumCase(ID, "scalable-predicate-vector",
382+
TargetStackID::ScalablePredicateVector);
382383
IO.enumCase(ID, "wasm-local", TargetStackID::WasmLocal);
383384
IO.enumCase(ID, "noalloc", TargetStackID::NoAlloc);
384385
}

‎llvm/include/llvm/CodeGen/MachineFrameInfo.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -495,13 +495,13 @@ class MachineFrameInfo {
495495
bool contributesToMaxAlignment(uint8_t StackID) {
496496
return StackID == TargetStackID::Default ||
497497
StackID == TargetStackID::ScalableVector ||
498-
StackID == TargetStackID::ScalablePredVector;
498+
StackID == TargetStackID::ScalablePredicateVector;
499499
}
500500

501501
bool isScalableStackID(int ObjectIdx) const {
502502
uint8_t StackID = getStackID(ObjectIdx);
503503
return StackID == TargetStackID::ScalableVector ||
504-
StackID == TargetStackID::ScalablePredVector;
504+
StackID == TargetStackID::ScalablePredicateVector;
505505
}
506506

507507
/// setObjectAlignment - Change the alignment of the specified stack object.

‎llvm/include/llvm/CodeGen/TargetFrameLowering.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ enum Value {
3232
SGPRSpill = 1,
3333
ScalableVector = 2,
3434
WasmLocal = 3,
35-
ScalablePredVector = 4,
35+
ScalablePredicateVector = 4,
3636
NoAlloc = 255
3737
};
3838
}

‎llvm/lib/Target/AArch64/AArch64FrameLowering.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3691,9 +3691,9 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
36913691
if (RPI.isPaired())
36923692
MFI.setStackID(FrameIdxReg2, TargetStackID::ScalableVector);
36933693
} else if (RPI.Type == RegPairInfo::PPR) {
3694-
MFI.setStackID(FrameIdxReg1, TargetStackID::ScalablePredVector);
3694+
MFI.setStackID(FrameIdxReg1, TargetStackID::ScalablePredicateVector);
36953695
if (RPI.isPaired())
3696-
MFI.setStackID(FrameIdxReg2, TargetStackID::ScalablePredVector);
3696+
MFI.setStackID(FrameIdxReg2, TargetStackID::ScalablePredicateVector);
36973697
}
36983698
}
36993699
return true;

‎llvm/lib/Target/AArch64/AArch64FrameLowering.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -119,7 +119,7 @@ class AArch64FrameLowering : public TargetFrameLowering {
119119
return false;
120120
case TargetStackID::Default:
121121
case TargetStackID::ScalableVector:
122-
case TargetStackID::ScalablePredVector:
122+
case TargetStackID::ScalablePredicateVector:
123123
case TargetStackID::NoAlloc:
124124
return true;
125125
}
@@ -129,7 +129,7 @@ class AArch64FrameLowering : public TargetFrameLowering {
129129
// We don't support putting SVE objects into the pre-allocated local
130130
// frame block at the moment.
131131
return (StackId != TargetStackID::ScalableVector &&
132-
StackId != TargetStackID::ScalablePredVector);
132+
StackId != TargetStackID::ScalablePredicateVector);
133133
}
134134

135135
void

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9534,7 +9534,7 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
95349534
if (isScalable) {
95359535
bool IsPred = VA.getValVT() == MVT::aarch64svcount ||
95369536
VA.getValVT().getVectorElementType() == MVT::i1;
9537-
MFI.setStackID(FI, IsPred ? TargetStackID::ScalablePredVector
9537+
MFI.setStackID(FI, IsPred ? TargetStackID::ScalablePredicateVector
95389538
: TargetStackID::ScalableVector);
95399539
}
95409540

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5572,7 +5572,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
55725572
assert(Subtarget.isSVEorStreamingSVEAvailable() &&
55735573
"Unexpected register store without SVE store instructions");
55745574
Opc = AArch64::STR_PXI;
5575-
StackID = TargetStackID::ScalablePredVector;
5575+
StackID = TargetStackID::ScalablePredicateVector;
55765576
}
55775577
break;
55785578
}
@@ -5587,7 +5587,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
55875587
Opc = AArch64::STRSui;
55885588
else if (AArch64::PPR2RegClass.hasSubClassEq(RC)) {
55895589
Opc = AArch64::STR_PPXI;
5590-
StackID = TargetStackID::ScalablePredVector;
5590+
StackID = TargetStackID::ScalablePredicateVector;
55915591
}
55925592
break;
55935593
case 8:
@@ -5757,7 +5757,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
57575757
if (IsPNR)
57585758
PNRReg = DestReg;
57595759
Opc = AArch64::LDR_PXI;
5760-
StackID = TargetStackID::ScalablePredVector;
5760+
StackID = TargetStackID::ScalablePredicateVector;
57615761
}
57625762
break;
57635763
}
@@ -5772,7 +5772,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
57725772
Opc = AArch64::LDRSui;
57735773
else if (AArch64::PPR2RegClass.hasSubClassEq(RC)) {
57745774
Opc = AArch64::LDR_PPXI;
5775-
StackID = TargetStackID::ScalablePredVector;
5775+
StackID = TargetStackID::ScalablePredicateVector;
57765776
}
57775777
break;
57785778
case 8:

‎llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -164,10 +164,10 @@ stack:
164164
- { id: 1, name: z1.addr, size: 16, alignment: 16, stack-id: scalable-vector,
165165
debug-info-variable: '!31', debug-info-expression: '!DIExpression()',
166166
debug-info-location: '!32' }
167-
- { id: 2, name: p0.addr, size: 2, alignment: 2, stack-id: scalable-pred-vector,
167+
- { id: 2, name: p0.addr, size: 2, alignment: 2, stack-id: scalable-predicate-vector,
168168
debug-info-variable: '!33', debug-info-expression: '!DIExpression()',
169169
debug-info-location: '!34' }
170-
- { id: 3, name: p1.addr, size: 2, alignment: 2, stack-id: scalable-pred-vector,
170+
- { id: 3, name: p1.addr, size: 2, alignment: 2, stack-id: scalable-predicate-vector,
171171
debug-info-variable: '!35', debug-info-expression: '!DIExpression()',
172172
debug-info-location: '!36' }
173173
- { id: 4, name: w0.addr, size: 4, alignment: 4, local-offset: -4, debug-info-variable: '!37',
@@ -181,10 +181,10 @@ stack:
181181
- { id: 7, name: localv1, size: 16, alignment: 16, stack-id: scalable-vector,
182182
debug-info-variable: '!45', debug-info-expression: '!DIExpression()',
183183
debug-info-location: '!46' }
184-
- { id: 8, name: localp0, size: 2, alignment: 2, stack-id: scalable-pred-vector,
184+
- { id: 8, name: localp0, size: 2, alignment: 2, stack-id: scalable-predicate-vector,
185185
debug-info-variable: '!48', debug-info-expression: '!DIExpression()',
186186
debug-info-location: '!49' }
187-
- { id: 9, name: localp1, size: 2, alignment: 2, stack-id: scalable-pred-vector,
187+
- { id: 9, name: localp1, size: 2, alignment: 2, stack-id: scalable-predicate-vector,
188188
debug-info-variable: '!51', debug-info-expression: '!DIExpression()',
189189
debug-info-location: '!52' }
190190
machineFunctionInfo: {}

‎llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -96,8 +96,8 @@ stack:
9696
- { id: 1, size: 8, alignment: 8 }
9797
- { id: 2, size: 16, alignment: 16, stack-id: scalable-vector }
9898
- { id: 3, size: 16, alignment: 16, stack-id: scalable-vector }
99-
- { id: 4, size: 2, alignment: 2, stack-id: scalable-pred-vector }
100-
- { id: 5, size: 2, alignment: 2, stack-id: scalable-pred-vector }
99+
- { id: 4, size: 2, alignment: 2, stack-id: scalable-predicate-vector }
100+
- { id: 5, size: 2, alignment: 2, stack-id: scalable-predicate-vector }
101101
machineFunctionInfo: {}
102102
body: |
103103
bb.0.entry:

‎llvm/test/CodeGen/AArch64/framelayout-sve.mir‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1215,19 +1215,19 @@ body: |
12151215
# CHECK: - { id: 2, name: '', type: default, offset: -112, size: 16, alignment: 16,
12161216
# CHECK-NEXT: stack-id: scalable-vector,
12171217
# CHECK: - { id: 3, name: '', type: default, offset: -114, size: 2, alignment: 2,
1218-
# CHECK-NEXT: stack-id: scalable-pred-vector,
1218+
# CHECK-NEXT: stack-id: scalable-predicate-vector,
12191219
# CHECK: - { id: 4, name: '', type: spill-slot, offset: -144, size: 16, alignment: 16,
12201220
# CHECK-NEXT: stack-id: scalable-vector,
12211221
# CHECK: - { id: 5, name: '', type: spill-slot, offset: -146, size: 2, alignment: 2,
1222-
# CHECK-NEXT: stack-id: scalable-pred-vector,
1222+
# CHECK-NEXT: stack-id: scalable-predicate-vector,
12231223
# CHECK: - { id: 6, name: '', type: spill-slot, offset: -16, size: 16, alignment: 16,
12241224
# CHECK-NEXT: stack-id: scalable-vector, callee-saved-register: '$z8',
12251225
# CHECK: - { id: 7, name: '', type: spill-slot, offset: -32, size: 16, alignment: 16,
12261226
# CHECK-NEXT: stack-id: scalable-vector, callee-saved-register: '$z23',
12271227
# CHECK: - { id: 8, name: '', type: spill-slot, offset: -34, size: 2, alignment: 2,
1228-
# CHECK-NEXT: stack-id: scalable-pred-vector, callee-saved-register: '$p4',
1228+
# CHECK-NEXT: stack-id: scalable-predicate-vector, callee-saved-register: '$p4',
12291229
# CHECK: - { id: 9, name: '', type: spill-slot, offset: -36, size: 2, alignment: 2,
1230-
# CHECK-NEXT: stack-id: scalable-pred-vector, callee-saved-register: '$p15',
1230+
# CHECK-NEXT: stack-id: scalable-predicate-vector, callee-saved-register: '$p15',
12311231
# CHECK: - { id: 10, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
12321232
# CHECK-NEXT: stack-id: default, callee-saved-register: '$fp',
12331233
#
@@ -1295,9 +1295,9 @@ stack:
12951295
- { id: 0, type: default, size: 32, alignment: 16, stack-id: scalable-vector }
12961296
- { id: 1, type: default, size: 4, alignment: 2, stack-id: scalable-vector }
12971297
- { id: 2, type: default, size: 16, alignment: 16, stack-id: scalable-vector }
1298-
- { id: 3, type: default, size: 2, alignment: 2, stack-id: scalable-pred-vector }
1298+
- { id: 3, type: default, size: 2, alignment: 2, stack-id: scalable-predicate-vector }
12991299
- { id: 4, type: spill-slot, size: 16, alignment: 16, stack-id: scalable-vector }
1300-
- { id: 5, type: spill-slot, size: 2, alignment: 2, stack-id: scalable-pred-vector }
1300+
- { id: 5, type: spill-slot, size: 2, alignment: 2, stack-id: scalable-predicate-vector }
13011301
body: |
13021302
bb.0.entry:
13031303

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