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+4
-114
lines changed

2 files changed

+4
-114
lines changed

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2822,13 +2822,13 @@ SDValue SITargetLowering::LowerFormalArguments(
28222822
const Function &Fn = MF.getFunction();
28232823
FunctionType *FType = MF.getFunction().getFunctionType();
28242824
SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
2825-
bool IsUnsupportedHsa = false;
2825+
bool IsError = false;
28262826

28272827
if (Subtarget->isAmdHsaOS() && AMDGPU::isGraphics(CallConv)) {
28282828
DiagnosticInfoUnsupported NoGraphicsHSA(
28292829
Fn, "unsupported non-compute shaders with HSA", DL.getDebugLoc());
28302830
DAG.getContext()->diagnose(NoGraphicsHSA);
2831-
IsUnsupportedHsa = true;
2831+
IsError = true;
28322832
}
28332833

28342834
SmallVector<ISD::InputArg, 16> Splits;
@@ -2937,8 +2937,7 @@ SDValue SITargetLowering::LowerFormalArguments(
29372937

29382938
for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
29392939
const ISD::InputArg &Arg = Ins[i];
2940-
if ((Arg.isOrigArg() && Skipped[Arg.getOrigArgIndex()]) ||
2941-
IsUnsupportedHsa) {
2940+
if ((Arg.isOrigArg() && Skipped[Arg.getOrigArgIndex()]) || IsError) {
29422941
InVals.push_back(DAG.getUNDEF(Arg.VT));
29432942
continue;
29442943
}

‎llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll‎

Lines changed: 1 addition & 110 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,4 @@
1-
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --tool not --version 5
2-
; RUN: not llc -mtriple=amdgcn-unknown-amdhsa -O0 -stop-after=amdgpu-isel -o - < %s 2>&1 | FileCheck %s
1+
; RUN: not llc -mtriple=amdgcn-unknown-amdhsa -O0 -filetype=null < %s 2>&1 | FileCheck %s
32

43
@I = global i32 42
54
@P = global ptr @I
@@ -14,160 +13,52 @@
1413
; CHECK: error: <unknown>:0:0: in function geometry_shader_one_arg void (ptr): unsupported non-compute shaders with HSA
1514
; CHECK: error: <unknown>:0:0: in function geometry_shader_two_args void (ptr, i32): unsupported non-compute shaders with HSA
1615

17-
; CHECK-LABEL: name: pixel_shader_zero_args
18-
; CHECK: bb.0 (%ir-block.0):
19-
; CHECK-NEXT: %2:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @I, target-flags(amdgpu-gotprel32-hi) @I, implicit-def dead $scc
20-
; CHECK-NEXT: %3:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed %2, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
21-
; CHECK-NEXT: %5:vreg_64 = COPY %3
22-
; CHECK-NEXT: %4:vgpr_32 = FLAT_LOAD_DWORD killed %5, 0, 0, implicit $exec, implicit $flat_scr :: (dereferenceable load (s32) from @I)
23-
; CHECK-NEXT: %6:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @P, target-flags(amdgpu-gotprel32-hi) @P, implicit-def dead $scc
24-
; CHECK-NEXT: %7:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed %6, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
25-
; CHECK-NEXT: %8:vreg_64 = COPY %7
26-
; CHECK-NEXT: FLAT_STORE_DWORD killed %8, killed %4, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into @P)
27-
; CHECK-NEXT: S_ENDPGM 0
2816
define amdgpu_ps void @pixel_shader_zero_args() {
2917
%i = load i32, ptr @I
3018
store i32 %i, ptr @P
3119
ret void
3220
}
3321

34-
; CHECK-LABEL: name: pixel_shader_one_arg
35-
; CHECK: bb.0 (%ir-block.0):
36-
; CHECK-NEXT: %4:sreg_32 = IMPLICIT_DEF
37-
; CHECK-NEXT: %5:sreg_32 = IMPLICIT_DEF
38-
; CHECK-NEXT: %6:sreg_32 = IMPLICIT_DEF
39-
; CHECK-NEXT: %7:sreg_32 = IMPLICIT_DEF
40-
; CHECK-NEXT: %3:sreg_64 = REG_SEQUENCE %4, %subreg.sub0, %6, %subreg.sub1
41-
; CHECK-NEXT: %2:vreg_64 = COPY %3
42-
; CHECK-NEXT: %8:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @I, target-flags(amdgpu-gotprel32-hi) @I, implicit-def dead $scc
43-
; CHECK-NEXT: %9:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed %8, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
44-
; CHECK-NEXT: %11:vreg_64 = COPY %9
45-
; CHECK-NEXT: %10:vgpr_32 = FLAT_LOAD_DWORD killed %11, 0, 0, implicit $exec, implicit $flat_scr :: (dereferenceable load (s32) from @I)
46-
; CHECK-NEXT: %12:vreg_64 = COPY %3
47-
; CHECK-NEXT: FLAT_STORE_DWORD %12, killed %10, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.p)
48-
; CHECK-NEXT: S_ENDPGM 0
4922
define amdgpu_ps void @pixel_shader_one_arg(ptr %p) {
5023
%i = load i32, ptr @I
5124
store i32 %i, ptr %p
5225
ret void
5326
}
5427

55-
; CHECK-LABEL: name: pixel_shader_two_args
56-
; CHECK: bb.0 (%ir-block.0):
57-
; CHECK-NEXT: %5:sreg_32 = IMPLICIT_DEF
58-
; CHECK-NEXT: %6:sreg_32 = IMPLICIT_DEF
59-
; CHECK-NEXT: %7:sreg_32 = IMPLICIT_DEF
60-
; CHECK-NEXT: %8:sreg_32 = IMPLICIT_DEF
61-
; CHECK-NEXT: %4:sreg_64 = REG_SEQUENCE %5, %subreg.sub0, %7, %subreg.sub1
62-
; CHECK-NEXT: %3:vgpr_32 = IMPLICIT_DEF
63-
; CHECK-NEXT: %2:vreg_64 = COPY %4
64-
; CHECK-NEXT: S_ENDPGM 0
6528
define amdgpu_ps void @pixel_shader_two_args(ptr %p, i32 %i) {
6629
store i32 %i, ptr %p
6730
ret void
6831
}
6932

70-
; CHECK-LABEL: name: vertex_shader_zero_args
71-
; CHECK: bb.0 (%ir-block.0):
72-
; CHECK-NEXT: %2:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @I, target-flags(amdgpu-gotprel32-hi) @I, implicit-def dead $scc
73-
; CHECK-NEXT: %3:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed %2, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
74-
; CHECK-NEXT: %5:vreg_64 = COPY %3
75-
; CHECK-NEXT: %4:vgpr_32 = FLAT_LOAD_DWORD killed %5, 0, 0, implicit $exec, implicit $flat_scr :: (dereferenceable load (s32) from @I)
76-
; CHECK-NEXT: %6:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @P, target-flags(amdgpu-gotprel32-hi) @P, implicit-def dead $scc
77-
; CHECK-NEXT: %7:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed %6, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
78-
; CHECK-NEXT: %8:vreg_64 = COPY %7
79-
; CHECK-NEXT: FLAT_STORE_DWORD killed %8, killed %4, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into @P)
80-
; CHECK-NEXT: S_ENDPGM 0
8133
define amdgpu_vs void @vertex_shader_zero_args() {
8234
%i = load i32, ptr @I
8335
store i32 %i, ptr @P
8436
ret void
8537
}
8638

87-
; CHECK-LABEL: name: vertex_shader_one_arg
88-
; CHECK: bb.0 (%ir-block.0):
89-
; CHECK-NEXT: %4:sreg_32 = IMPLICIT_DEF
90-
; CHECK-NEXT: %5:sreg_32 = IMPLICIT_DEF
91-
; CHECK-NEXT: %6:sreg_32 = IMPLICIT_DEF
92-
; CHECK-NEXT: %7:sreg_32 = IMPLICIT_DEF
93-
; CHECK-NEXT: %3:sreg_64 = REG_SEQUENCE %4, %subreg.sub0, %6, %subreg.sub1
94-
; CHECK-NEXT: %2:vreg_64 = COPY %3
95-
; CHECK-NEXT: %8:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @I, target-flags(amdgpu-gotprel32-hi) @I, implicit-def dead $scc
96-
; CHECK-NEXT: %9:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed %8, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
97-
; CHECK-NEXT: %11:vreg_64 = COPY %9
98-
; CHECK-NEXT: %10:vgpr_32 = FLAT_LOAD_DWORD killed %11, 0, 0, implicit $exec, implicit $flat_scr :: (dereferenceable load (s32) from @I)
99-
; CHECK-NEXT: %12:vreg_64 = COPY %3
100-
; CHECK-NEXT: FLAT_STORE_DWORD %12, killed %10, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.p)
101-
; CHECK-NEXT: S_ENDPGM 0
10239
define amdgpu_vs void @vertex_shader_one_arg(ptr %p) {
10340
%i = load i32, ptr @I
10441
store i32 %i, ptr %p
10542
ret void
10643
}
10744

108-
; CHECK-LABEL: name: vertex_shader_two_args
109-
; CHECK: bb.0 (%ir-block.0):
110-
; CHECK-NEXT: %5:sreg_32 = IMPLICIT_DEF
111-
; CHECK-NEXT: %6:sreg_32 = IMPLICIT_DEF
112-
; CHECK-NEXT: %7:sreg_32 = IMPLICIT_DEF
113-
; CHECK-NEXT: %8:sreg_32 = IMPLICIT_DEF
114-
; CHECK-NEXT: %4:sreg_64 = REG_SEQUENCE %5, %subreg.sub0, %7, %subreg.sub1
115-
; CHECK-NEXT: %3:vgpr_32 = IMPLICIT_DEF
116-
; CHECK-NEXT: %2:vreg_64 = COPY %4
117-
; CHECK-NEXT: S_ENDPGM 0
11845
define amdgpu_vs void @vertex_shader_two_args(ptr %p, i32 %i) {
11946
store i32 %i, ptr %p
12047
ret void
12148
}
12249

123-
; CHECK-LABEL: name: geometry_shader_zero_args
124-
; CHECK: bb.0 (%ir-block.0):
125-
; CHECK-NEXT: %2:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @I, target-flags(amdgpu-gotprel32-hi) @I, implicit-def dead $scc
126-
; CHECK-NEXT: %3:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed %2, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
127-
; CHECK-NEXT: %5:vreg_64 = COPY %3
128-
; CHECK-NEXT: %4:vgpr_32 = FLAT_LOAD_DWORD killed %5, 0, 0, implicit $exec, implicit $flat_scr :: (dereferenceable load (s32) from @I)
129-
; CHECK-NEXT: %6:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @P, target-flags(amdgpu-gotprel32-hi) @P, implicit-def dead $scc
130-
; CHECK-NEXT: %7:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed %6, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
131-
; CHECK-NEXT: %8:vreg_64 = COPY %7
132-
; CHECK-NEXT: FLAT_STORE_DWORD killed %8, killed %4, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into @P)
133-
; CHECK-NEXT: S_ENDPGM 0
13450
define amdgpu_gs void @geometry_shader_zero_args() {
13551
%i = load i32, ptr @I
13652
store i32 %i, ptr @P
13753
ret void
13854
}
13955

140-
; CHECK-LABEL: name: geometry_shader_one_arg
141-
; CHECK: bb.0 (%ir-block.0):
142-
; CHECK-NEXT: %4:sreg_32 = IMPLICIT_DEF
143-
; CHECK-NEXT: %5:sreg_32 = IMPLICIT_DEF
144-
; CHECK-NEXT: %6:sreg_32 = IMPLICIT_DEF
145-
; CHECK-NEXT: %7:sreg_32 = IMPLICIT_DEF
146-
; CHECK-NEXT: %3:sreg_64 = REG_SEQUENCE %4, %subreg.sub0, %6, %subreg.sub1
147-
; CHECK-NEXT: %2:vreg_64 = COPY %3
148-
; CHECK-NEXT: %8:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @I, target-flags(amdgpu-gotprel32-hi) @I, implicit-def dead $scc
149-
; CHECK-NEXT: %9:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed %8, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
150-
; CHECK-NEXT: %11:vreg_64 = COPY %9
151-
; CHECK-NEXT: %10:vgpr_32 = FLAT_LOAD_DWORD killed %11, 0, 0, implicit $exec, implicit $flat_scr :: (dereferenceable load (s32) from @I)
152-
; CHECK-NEXT: %12:vreg_64 = COPY %3
153-
; CHECK-NEXT: FLAT_STORE_DWORD %12, killed %10, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.p)
154-
; CHECK-NEXT: S_ENDPGM 0
15556
define amdgpu_gs void @geometry_shader_one_arg(ptr %p) {
15657
%i = load i32, ptr @I
15758
store i32 %i, ptr %p
15859
ret void
15960
}
16061

161-
; CHECK-LABEL: name: geometry_shader_two_args
162-
; CHECK: bb.0 (%ir-block.0):
163-
; CHECK-NEXT: %5:sreg_32 = IMPLICIT_DEF
164-
; CHECK-NEXT: %6:sreg_32 = IMPLICIT_DEF
165-
; CHECK-NEXT: %7:sreg_32 = IMPLICIT_DEF
166-
; CHECK-NEXT: %8:sreg_32 = IMPLICIT_DEF
167-
; CHECK-NEXT: %4:sreg_64 = REG_SEQUENCE %5, %subreg.sub0, %7, %subreg.sub1
168-
; CHECK-NEXT: %3:vgpr_32 = IMPLICIT_DEF
169-
; CHECK-NEXT: %2:vreg_64 = COPY %4
170-
; CHECK-NEXT: S_ENDPGM 0
17162
define amdgpu_gs void @geometry_shader_two_args(ptr %p, i32 %i) {
17263
store i32 %i, ptr %p
17364
ret void

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