Review feedback

Author: dakersnar

llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp

@@ -3230,10 +3230,9 @@ static SDValue lowerMSTORE(SDValue Op, SelectionDAG &DAG) {
   assert(Mask.getValueType().getVectorNumElements() ==
              ValVT.getVectorNumElements() &&
          "Mask size must be the same as the vector size");
-  for (unsigned I : llvm::seq(ValVT.getVectorNumElements())) {
-    assert(isa<ConstantSDNode>(Mask.getOperand(I)) &&
-           "Mask elements must be constants");
-    if (Mask->getConstantOperandVal(I) == 0) {
+  for (auto [I, Op] : enumerate(Mask->ops())) {
+    // Mask elements must be constants.
+    if (Op.getNode()->getAsZExtVal() == 0) {
       // Append a sentinel register 0 to the Ops vector to represent a masked
       // off element, this will be handled in tablegen
       Ops.push_back(DAG.getRegister(MCRegister::NoRegister,
@@ -3501,7 +3500,7 @@ SDValue NVPTXTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
                       MachinePointerInfo(SV));
 }
 
-static std::tuple<MemSDNode *, uint32_t>
+static std::pair<MemSDNode *, uint32_t>
 convertMLOADToLoadWithUsedBytesMask(MemSDNode *N, SelectionDAG &DAG) {
   SDValue Chain = N->getOperand(0);
   SDValue BasePtr = N->getOperand(1);
@@ -3526,16 +3525,14 @@ convertMLOADToLoadWithUsedBytesMask(MemSDNode *N, SelectionDAG &DAG) {
   uint32_t ElementSizeInBytes = ElementSizeInBits / 8;
   uint32_t ElementMask = (1u << ElementSizeInBytes) - 1u;
 
-  for (unsigned I :
-       llvm::reverse(llvm::seq<unsigned>(0, ResVT.getVectorNumElements()))) {
-    assert(isa<ConstantSDNode>(Mask.getOperand(I)) &&
-           "Mask elements must be constants");
-    // We technically only want to do this shift for every iteration *but* the
-    // first, but in the first iteration NewMask is 0, so this shift is a
-    // no-op.
+  for (SDValue Op : llvm::reverse(Mask->ops())) {
+    // We technically only want to do this shift for every
+    // iteration *but* the first, but in the first iteration NewMask is 0, so
+    // this shift is a no-op.
     UsedBytesMask <<= ElementSizeInBytes;
 
-    if (Mask->getConstantOperandVal(I) != 0)
+    // Mask elements must be constants.
+    if (Op->getAsZExtVal() != 0)
       UsedBytesMask |= ElementMask;
   }
 
@@ -3581,11 +3578,8 @@ replaceLoadVector(SDNode *N, SelectionDAG &DAG, const NVPTXSubtarget &STI) {
 
   // If we have a masked load, convert it to a normal load now
   std::optional<uint32_t> UsedBytesMask = std::nullopt;
-  if (LD->getOpcode() == ISD::MLOAD) {
-    auto Result = convertMLOADToLoadWithUsedBytesMask(LD, DAG);
-    LD = std::get<0>(Result);
-    UsedBytesMask = std::get<1>(Result);
-  }
+  if (LD->getOpcode() == ISD::MLOAD)
+    std::tie(LD, UsedBytesMask) = convertMLOADToLoadWithUsedBytesMask(LD, DAG);
 
   // Since LoadV2 is a target node, we cannot rely on DAG type legalization.
   // Therefore, we must ensure the type is legal.  For i1 and i8, we set the

llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp

@@ -610,12 +610,9 @@ bool NVPTXTTIImpl::isLegalMaskedStore(Type *DataTy, Align Alignment,
   if (!VTy)
     return false;
 
-  auto *ScalarTy = VTy->getScalarType();
-  if ((ScalarTy->getScalarSizeInBits() == 32 && VTy->getNumElements() == 8) ||
-      (ScalarTy->getScalarSizeInBits() == 64 && VTy->getNumElements() == 4))
-    return true;
-
-  return false;
+  auto *ElemTy = VTy->getScalarType();
+  return (ElemTy->getScalarSizeInBits() == 32 && VTy->getNumElements() == 8) ||
+         (ElemTy->getScalarSizeInBits() == 64 && VTy->getNumElements() == 4);
 }
 
 bool NVPTXTTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment,