address comments

Author: moar55

clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp

@@ -89,9 +89,9 @@ static mlir::Value getMaskVecValue(CIRGenBuilderTy &builder, mlir::Location loc,
 }
 
 static mlir::Value emitX86FunnelShift(CIRGenFunction &cgf,
-                                      const mlir::Location &location,
-                                      mlir::Value &op0, mlir::Value &op1,
-                                      mlir::Value &amt, bool isRight) {
+                                      mlir::Location location, mlir::Value &op0,
+                                      mlir::Value &op1, mlir::Value &amt,
+                                      bool isRight) {
   CIRGenBuilderTy &builder = cgf.getBuilder();
   mlir::Type op0Ty = op0.getType();
 

clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c

@@ -79,13 +79,30 @@ __m512i test_mm512_undefined_epi32(void) {
 }
 
 __m512i test_mm512_ror_epi32(__m512i __A) {
-  // CHECK-LABEL: test_mm512_ror_epi32
-  // CHECK: @llvm.fshr.v16i32
+  // CIR-LABEL: test_mm512_ror_epi32
+  // CIR: {{%.*}} =  cir.cast integral {{%.*}} : !s32i -> !u32i
+  // CIR: {{%.*}} = cir.vec.splat {{%.*}} : !u32i, !cir.vector<16 x !u32i>
+  // CIR: {{%.*}} = cir.call_llvm_intrinsic "fshr" {{%.*}}: (!cir.vector<16 x !s32i>, !cir.vector<16 x !s32i>, !cir.vector<16 x !u32i>) -> !cir.vector<16 x !s32i> 
+  // LLVM-LABEL: test_mm512_ror_epi32
+  // LLVM: %[[CASTED_VAR:.*]] = bitcast <8 x i64> {{%.*}} to <16 x i32>
+  // LLVM: {{%.*}} = call <16 x i32> @llvm.fshr.v16i32(<16 x i32> %[[CASTED_VAR]], <16 x i32> %[[CASTED_VAR]], <16 x i32> splat (i32 5))
+  // OGCG-LABEL: test_mm512_ror_epi32
+  // OGCG: %[[CASTED_VAR:.*]] = bitcast <8 x i64> {{%.*}} to <16 x i32>
+  // OGCG: {{%.*}} = call <16 x i32> @llvm.fshr.v16i32(<16 x i32> %[[CASTED_VAR]], <16 x i32> %[[CASTED_VAR]], <16 x i32> splat (i32 5))
   return _mm512_ror_epi32(__A, 5); 
 }
 
 __m512i test_mm512_ror_epi64(__m512i __A) {
-  // CHECK-LABEL: test_mm512_ror_epi64
-  // CHECK: @llvm.fshr.v8i64
+  // CIR-LABEL: test_mm512_ror_epi64
+  // CIR: {{%.*}} =  cir.cast integral {{%.*}} : !s32i -> !u32i
+  // CIR: {{%.*}} =  cir.cast integral {{%.*}} : !u32i -> !u64i
+  // CIR: {{%.*}} = cir.vec.splat {{%.*}} : !u64i, !cir.vector<8 x !u64i>
+  // CIR: {{%.*}} = cir.call_llvm_intrinsic "fshr" {{%.*}}: (!cir.vector<8 x !s64i>, !cir.vector<8 x !s64i>, !cir.vector<8 x !u64i>) -> !cir.vector<8 x !s64i> 
+  // LLVM-LABEL: test_mm512_ror_epi64
+  // LLVM: %[[VAR:.*]] = load <8 x i64>, ptr {{%.*}}, align 64
+  // LLVM: {{%.*}} = call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %[[VAR]], <8 x i64> %[[VAR]], <8 x i64> splat (i64 5))
+  // OGCG-LABEL: test_mm512_ror_epi64
+  // OGCG: %[[VAR:.*]] = load <8 x i64>, ptr {{%.*}}, align 64
+  // OGCG: {{%.*}} = call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %[[VAR]], <8 x i64> %[[VAR]], <8 x i64> splat (i64 5))
   return _mm512_ror_epi64(__A, 5); 
 }

clang/test/CodeGen/X86/xop-builtins.c

@@ -429,3 +429,10 @@ __m256d test_mm256_frcz_pd(__m256d a) {
   // CHECK: call {{.*}}<4 x double> @llvm.x86.xop.vfrcz.pd.256(<4 x double> %{{.*}})
   return _mm256_frcz_pd(a);
 }
+
+
+__m512i test_mm512_ror_epi32(__m512i __A) {
+  // CHECK-LABEL: test_mm512_ror_epi32
+  // CHECK: @llvm.fshr.v16i32
+  return _mm512_ror_epi32(__A, 5); 
+}